UVM Verification Engineer
Website CEVA
Description
Are you interested in the IoT world? Does a dynamic team from an established and high-end business unit excite you?
Then you will find your place with us!
Within the Wireless Internet of Things Business Unit, you will be a member of our UWB (Ultra-Wideband) team.
As part of our IoT department, you will take an active role in the future evolution of our UWB IP (Intellectual Property).
Your responsibilities will involve:
- Reporting to the HW Manager, you will be part of the UWB UVM team and be part of the IoT development Team.
- Working closely with signal processing and digital design teams.
Requirements
- Experience as UVM engineer
- 3-5+ years’ experience of the design and/or verification of RTL (Verilog)
- Advanced knowledge of UVM, System Verilog, Constrained Random simulation, and coverage definition.
- Strong knowledge of object oriented programming features
- Good debug skills
The following skills are considered as a plus:
- Knowledge in Wireless communication systems (Cellular, WiFi, BT)
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