Work with corporate library team within TMSC to define and deliver state-of-the-art standard cell libraries that will make a difference in the overall block PPA needs of various TSMC customers. You will be working with a team of hardworking engineers to come up with new library insights and work towards integrating them into a chip. Responsibilities include (but not limited to)
Define and develop new standard/semi-custom library cells that can significantly boost circuit performance in advanced nanometer technologies
Develop variation tolerant robust circuits that can reliably operate at low VCC
Identify circuit techniques that systematically reduce power consumption
Engage with customers to understand new library requirements and identify PPA knobs through generic and/or custom solutions.
Perform timing, power, EMIR analysis and mitigate concerns through innovative solutions.
Work closely with EDA vendors to develop and demonstrate value in new library cell design concepts for improved block PPA.
Be a strong team player.
M.S. or Ph.D. in Electrical or Computer Engineering with coursework in VLSI and/or Digital Design.
Good clarity in transistor level design, analysis, and optimization.
Very clear understanding with at least 5+ years of hands-on experience on key standard cell design concepts and ability to do insightful library design tradeoffs in terms of power, set-up, hold, pin hits, pin caps, cell area, noise ratio, slew, and leakage.
Ability to link the standard cell library design parameters to anticipated block PPA impact is crucial.
Able to use industry standard tools in designing standard cell circuits and layouts
Experience in design automation using TCL/Perl/Python and EDA tool flow automation.
Good understanding of cell characterization, library validation flows with knowledge in power, noise and IR analysis.
Must have good communication skills with the intellectual curiosity to debug/root cause of difficult problems and strong problem solving skills with an innovative mindset.