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Sr Principal Design Engineer

Sr Principal Design Engineer
by Admin on 02-20-2023 at 9:11 pm

Website Cadence

Position Description:

Deliver/implement SoC and ASIC chip. The engineer should be able to act as a good team member/leader

Specific duties include:

  • Proficiency in SoC and ASIC spec definition, micro-architecture bring-up, RTL coding, synthesis, STA and testing
  • Proficiency in SoC and ASIC design flow and sign-off, especially front-end
  • Frontend technical and team leader for successful SoC/ASIC chip tape-out

Position Requirements:

  • Master degree with 10+ years as an experienced SoC front-end design technical leader
  • Expertise in micro-architecture bring-up and Verilog RTL digital design in SoC and ASIC chips in 28nm deep submicron technologies and beyond
  • Experienced in using STA, DFT and formal check tools
  • Experienced in successful tape-out of SoC/ASIC chips
  • Good knowledge and understanding on high performance / low power SOC and ASIC design, verification and power/timing
  • Self-motivation with communication skills (spoken and written English and Mandarin)
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To view the job application please visit

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