Senior VLSI Verification Engineer

Description

proteanTecs is a dynamic fast-paced start-up company, transforming the way reliability of electronics is achieved. In a world where machines are gaining immense responsibility over our lives, sudden failure is not an option.

We have developed a cloud-based platform, which combines data created in chip-embedded Agents (IPs), with machine learning, to predict faults before they become failures. Our solutions provide unprecedented insights throughout the value chain, from Chip Vendors to System Vendors and Digital Service Providers.

The company was founded by seasoned industry veterans, including three former founders of Mellanox Technologies, with deep knowledge and experience in the electronics industry and is backed by worldwide leading investors.

At proteanTecs we combine different disciplines to create a revolutionary solution. Our team is highly interdisciplinary, ranging from SaaS and Machine Learning experts, to top designers in Chips and Circuits, as well as masters of EDA. We work together and learn from each other.

We are looking for the best Senior VLSI Verification Engineer, TL to join the ride as we spearhead the next revolution in electronics.

Requirements

• B.Sc. in Electrical/Computer Engineering
• More than 7 years of experience as a VLSI Verification engineer, including Leading and Mentoring positions
• Functional-Verification expertise using System-Verilog UVM
• Breadth of experience in VLSI verification process: from design-architecture definitions, through “RTL Freeze” & Tape-Out, to post-silicon bring-up
• Vast knowledge of verification paradigms & “know-hows”
• Team player with excellent communication & organization skills
• High level of English proficiency (both oral and written)

Advantages:

• Experience in verifying Cycle-Accurate & Mixed-Signal designs
• Experience in Formal Verification
• Experience with verification using an Emulation environment
• Familiarity with post-silicon testing environment
• Familiarity with Design-For-Test & Design-For-Debug methodologies and tools
• Close familiarity with python, Git, Unix-like environment
• Other VLSI Design background (frontend, backend, circuit, architecture)

Responsibilities

• Define, Develop and Maintain Verification methodology
• Own verification test-plan and signoff new IP releases
• Define, Develop and Guide the verification of IP, embedded in customers’ designs, through the VLSI development milestones (“RTL Freeze”, Tape-out, post-silicon preparations)
• Review and contribute to definitions and specifications of novel agents (IPs) that are at the core of proteanTecs solution
• Guide and Lead younger verification engineers
• Support proteanTecs’ Field Application Engineers in their endeavor to provide a smooth customer experience
• Constantly pursue Quality and Automation improvement

Personal skills

• Focus on what’s right rather than who’s right
• Strong emphasis on knowledge sharing and open communication
• Self-driven