Senior Verification Engineer

This position provides an exceptional opportunity for a highly motivated and experienced verification engineer to join the engaging, hardworking, and creative System IP team.

The latest and most advanced hardware design and verification methodologies are employed to create the System IPs that will enable the development of the next generation of compute solutions for every area of technology, from mobile phones, to servers, to autonomous vehicles.

About the team

The Arm Central Engineering – System IP team in Cambridge, is responsible for specifying, developing, and validating Arm CoreLink and CoreSight IP products that support inter-process communication, trace, and debug solutions that scale from real-time embedded to hyperscale cloud. We are looking for verification experts to join our team and play an integral role in developing technology that makes people’s lives better.

This role will be based at Arm’s corporate headquarters in the historic city of Cambridge, home to one of the world’s most renowned and oldest Universities. The city is a key driver of global innovation, and regularly features as one of the most desirable places to live in the UK. As Arm’s largest engineering centre, the Cambridge site is fortunate enough to be involved in development across all areas of Arm’s ever-growing product portfolio. As a Cambridge-based Arm employee, you will be surrounded by world-leading experts, and will have the opportunity to work with some of the very best engineers in the industry. If the challenge of working on our cutting-edge technology excites you, and you can meet the requirements of the job description below, we look forward to receiving your application!

What will you be accountable for?

For this role we are looking for engineers who can own the verification of a unit within a project through all phases of the design and verification flow. This includes:

• Working closely with the RTL design team to develop comprehensive verification strategies
• Creating and reviewing design verification documentation
• Designing and implementing SystemVerilog/UVM based verification IP and testbenches
• Improving existing testbenches to increase performance, quality and efficiency
• Testing and debugging Verilog RTL
• Defining and implementing functional coverage as well as enhancing the testbench to ensure coverage closure
• Planning and tracking tasks to meet the targets at the planned time
• Driving the execution to ensure the quality of the design work done along with on time delivery
• Coaching and mentoring junior engineers

Essential Skills and Experience

• Substantial experience of RTL verification for complex ASIC products
• Proficiency in a hardware verification language, preferably System Verilog / UVM
• Experience of development of coverage-driven constrained random test environments
• Exposure to all stages of the design cycle: initial concept, specification, implementation and testing, documentation and support
• Experience producing specifications and documentation describing complex designs
• Understanding of the fundamentals of computer architecture
• Strong communication skills and ability to work well as part of a team
• Some team leadership experience, including planning and managing tasks

Desirable Skills and Experience

• Practical experience of working on microprocessor or complex system interconnect and peripheral designs
• Experience of low power RTL design and verification
• Proficiency in scripting languages such as Python or Perl
• Strong software engineering skills including understanding of object-oriented programming, data structures, and algorithms
• Competency in a hardware design language, preferably Verilog
• Knowledge of formal verification techniques and tools
• Line management experience