Senior Hardware Verification Engineer
![ArterisIP](https://semiwiki.com/wp-content/uploads/job-manager-uploads/company_logo/2019/11/Arteris-IP-Logo-150x25.png)
Website ArterisIP
As a Senior Hardware Verification Engineer at Arteris, you will have opportunity to be part of a verification team with powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions.
You will join a proven-successful company, and be able to influence development environment, architecture, verification, and everything in-between.
Key Responsibilities:
- Definition, documentation, development, and execution of RTL verification test/coverage for extremely parametrized IPs in Python and C++ language, able to run on any available RTL simulator (Cadence, Synopsys, etc.).
- Maintain and enhance the verification flow, improve metrics, and increase automation.
- Implement verification components such as BFMs or monitors used in verification test benches
Experience Requirements / Qualifications:
- 7+ years of industry experience as a Verification engineer
- Understanding of Hardware RTL design and verification languages (VHDL, Verilog, SystemC, C++, Python, SystemVerilog)
- Strong experience in using and developing verification methods and infrastructure (VIPs, UVM, test benches, EDA tools)
- Experience in formal proof verification methodology is a plus
- Shell scripting
- Knowledge of interconnect technology is a plus
- Understanding of Hardware communication protocols (AMBA, OCP, others)
- Good written and verbal communication skills in both French and English
- Curious, autonomous, rigorous, and delivery-oriented with a commitment to quality and a thorough approach to the work.
- Proven ability to work well within a team
Education Requirements:
- Master’s degree
Has ASML Reached the Great Wall of China