R&D Power Grid Design and Sign-Off Engineer
Website TSMC
We are power grid design and sign-off team for digital design inside TSMC.
The mission is to develop power grid design and co-optimize with semiconductor process in advanced technology nodes for most updated commercial design contents (CPU, GPU, SoC, etc.).
Our power grid designs are references for worldwide 1st Tier design houses.
Responsibilities:
1.Develop power grid structure for most updated commercial design contents (CPU, GPU, SoC, etc.) and check IR/EM (Electron-Migration) performance
2.Provide design solutions for IR/EM and routing optimization
3.Co-work with process R&D for process tuning to achieve better PDN (Power Delivery Network) design
4.Support TSMC advanced process node test chip PDN sign-off checks, including PDN quality check, static/dynamic IR sign-off, and EM sign-off for successful chip tape-out
5.Provide guidance and suggestion to PnR (Place and Route) designer on PDN issue fixing
Qualifications
1.Master of Science in Electrical Engineering is required
2.Knowledge of Electronics, Circuitry, and Semiconductor Physics/Devices for PDN structure design and IR results analysis is required
3.Basic programming skills, such as Perl, Python, C++ for flow automation, data analysis, and results summary are required
4.Better to have digital design PnR experience from floorplan stage, placement, CTS (Clock Tree Synthesis) to routing stage
5.Being familiar with digital design PnR flow is preferred
6.Being familiar with SPICE (Simulation Program with Integrated Circuit Emphasis) and mixed-mode simulation is a plus
7.Fluent English in speaking and in writing
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