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R&D Engineer, II

R&D Engineer, II
by Admin on 11-16-2022 at 10:59 am

Website Synopsys


  • Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM:
  • Design architecture and circuit implementation, especially ultra high speed, ultra low power, or high density design portfolio.
  • Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification and validation.
  • Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation and full verification flow.
  • Perform bit cell development and bit cell verification and drive physical layout design and verification.
  • Provide support and/or perform other duties as assigned and required


  • Schedule own work flow
  • Normally receives little instruction on day-to-day work, general instructions on new assignments.
  • Demonstrates good judgment in selecting methods and techniques for obtaining solutions.

Skills Requirements:

  • Bachelors or Master’s degree, Electrical Engineering, Telecommunication or related fields
  • Proficient with CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction and knowledge of layout verification tools and debugging techniques.
  • Programming capability- C-Shell, Perl. C++ or Java script a plus
  • Excellent problem solving skills along with attention to details.
  • Can develop a document, report or presentation for a range of tasks
  • Microsoft Office: Word, Excel, PowerPoint, Shared point and Outlook
  • Self-motivated, self-directed, detailed oriented and well organized
  • Good problem solving and negotiation skills
  • Ability to lead/mentor trainees and junior engineers as well as manage projects.
  • Excellent command of English both verbal and written
  • Interpersonal communication and team working skills
  • Professionalism, Critical thinking, future goals focused
  • High commitment to continuous learning
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