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Principal Verification Engineer

Principal Verification Engineer
by Admin on 06-25-2024 at 2:10 pm

Website Flex Logix

Responsibilities

Candidate will be involved in functional verification of embedded FPGA cores as well as DSP and Inference AI IP.

Responsible for all aspects of verification including:

  • Serve as a verification leader for the organization
  • Possibly manage 1 or 2 verification engineers
  • Development of verification testbenches using SystemVerilog/UVM
  • Development of test plans and execution to plan and coverage goals
  • Development of coverage plans and metrics, drive coverage activities and test writing
  • Automation of the verification process
  • Gate-Level simulation and debug

Required Experience

  • BSEE/MSEE with at least 10+ years of relevant experience.
  • Expert in Verilog and SystemVerilog testbench design, stimulus, and debug
  • Proven ability to craft requirements and design specifications into test planor verification plan documentation and execute to plan and coverage goals
  • Strong scripting language skills such as Perl, Python, and csh for thepurposes of automation and management of large parallel simulation tasks
  • Hands-on experience with standard functional simulators like Questa,NCSIM or VCS
  • Experience running and debugging gate simulations
  • Excellent planning and progress tracking skills
  • Good written, in-person and remote communication skills

Desired skills:

  • Experience with DFT pattern verification and debug
  • Experience implementing formal verification flows
  • FPGA verification experience
  • Familiarity with continuous integration infrastructure such as Jenkins
Apply for job

To view the job application please visit flex-logix.com.

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