The Physical Verification R&D Software Engineering role is a multi-faceted position encapsulating a mix of expert-level physical verification software development, algorithm development, software debugging, performance optimization and accuracy analysis. R&D engineers collaborate with a large team of EDA professionals across multiple cultures to create and deliver best in class next generation software for physical IC application. The R&D engineering can work on complicated applications and interface them with other applications in a large suite of high connected applications to enable next-generation physical verification solutions with superior performance and usability. R&D engineers develop code that satisfies the requirements for successful semiconductor design deployment. On a continuous basis R&D engineers deploy their mastery of physical verification LVS / PERC applications, as well as physical implementation methodologies, to guide the accuracy, performance and functionality enhancements within the Cadence physical verification suite of products.
Desired Skills and Experience (with different levels of experience):
Senior Role in R&D
- 7+ years of experience in software development using C/C++, with a focus in working with complex algorithms and performance
- Must be a fast learner and must demonstrate strong aptitude for out-of-the-box thinking and problem solving.
- TCL language development experience in a large project is a plus, as is an experience in deck development for LVS or PERC (16nm or below).
- Experience in physical signoff methodologies within the Physical implementation environment would be an added advantage.
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To view the job application please visit cadence.wd1.myworkdayjobs.com.