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Principal Hardware Verification Engineer

Principal Hardware Verification Engineer
by Admin on 06-17-2024 at 4:55 pm

Website ArterisIP

Arteris enables engineering and design teams at the world’s most transformative brands to connect and integrate today’s system-on-chips (SoCs) that fuel modern innovation.

If you’ve held a smartphone, driven an electronic car, or powered up a smart TV, you’ve come in contact with what we do at Arteris. Here, the future is quite literally in your hands—and when it isn’t, chances are it is flying overhead in a drone, a satellite, or in the cloud at a datacenter!

As a Principal Hardware Verification Engineer at Arteris, you will be leading the development of next generation of Arteris IP solutions, enabling the design verification of extremely configurable digital interconnects.

We intend to revolutionize the way to design and verify SoC, and we are looking for engineering talents willing to expose themselves to new design and verification methodologies and ready to learn and grow their competences to both digital design verification and software development.

You will create innovative test benches in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You’ll be exposed to very last computing architecture and participate to the development of next generation interconnect networks.

You will join a proven-successful company and be able to shape the future of System on Chip design.

Key responsibilities:

  • Advanced UVM based test bench development and debugging.
  • Defining, documenting, developing, and executing RTL verification test/coverage at system level.
  • Performance verification and power-aware verification.
  • Triaging Regressions, Debugging RTL designs in Verilog and System Verilog.
  • Help improve and refine verification process, methodology, and metrics.

Experience requirements / qualifications:


  • 10-12+ years of experience in SoC/IP digital design & verification.
  • Verification flow enhancements using SW programming languages.
  • Strong RTL (Verilog) and UVM/C test bench debugging skills.
  • Experience integrating vendor provided VIPs for unit and system level verification.
  • Excellent problem solving, strong communication and teamwork skills.
  • Self-driven, able to work with minimum supervision.


  • Experience with Arm AMBA protocols.
  • Experience with digital HW generators, methodology and concept.

Education Requirements:

  • PhD or master’s degree in Computer Sciences or related field.
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To view the job application please visit www.arteris.com.

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