Principal Application Engineer – SW IC Verification

Position Description:

1. Work closely with the Sales team to identify and scope opportunities for Cadence SoC Verification solution.

2. Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.

3. Train, ramp-up and accompany customer projects.

4. Conduct basic and advanced trainings, presentations and demos as necessary. 5. Providing technical expertise to address clients’ queries, which need expert involvement.

6. Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement.

Position Requirements:

– A master’s degree is essential and 8+ years’ experience in IC design or verification.

– Design experience in Verilog/VHDL for IP or SoC chip level is desired

– Verification with knowledge of System Verilog/VHDL and HDL simulators

– Advanced Verification Methodology like UVM

– Familiar the popular high speed interface protocol, such as PCIe, USB, SATA, etc. – Strong verbal and written communication skills in English

– Strong teamwork skills with good human relationship