As a member of the Silicon Engineering Team, the Physical Design Engineer contributes to the implementation of advanced node SoC designs from netlist to tape out. Skills include floorplanning, clock design, place and route, static timing analysis, and physical verification.
Must be able to obtain and maintain a Department of Defense classified clearance.
Minimum 5 years experience with Cadence Digital Implementation tools or equivalent (Innovus, Tempus, Voltus, Pegasus). Project leadership experience a plus. Minimum BSEE, MSEE