GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.
Summary of Role:
This is an engineer position within the Technology Enablement department. You will be working with cross-functional teams on design-technology co-optimization (DTCO) to improve technology PPA.
Essential Responsibilities Include:
- Logic standard cell layout design:
- work with circuit designers to understand design requirements and layout impact on standard cells
- proficient interpretation of LVS and DRC reports and quick fix to deliver clean and robust layout
- test chip tape out verification with DRC, LVS, PM, DFM, EM, etc.
- eNVM test chip design:
- work with MRAM/RRAM designers to understand design specs
- design decoder, mux, control block, etc.
- power plan, power grid, route and verify chip top and dummy fill
- Work with benchmark team on library benchmark across technologies
- Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
- BS or MS in EE related field with 8+ years of experience in semiconductor industry
- 5+ years hands on experience in standard cell library layout design for submicron CMOS technologies.
- Understand RC trade-off and LLE effect in design-technology co-optimization for best PPA
- High-level proficiency with Virtuoso layout and Calibre DRC/LVS
- Engineering curiosity
- Experience with ICC2 and/or INNOVUS is preferred
- General understanding of semiconductor fabrication processes