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Intern – “Correct by Construction” Analog/RF Process Design Kits Leveraging Machine Learning

Intern – “Correct by Construction” Analog/RF Process Design Kits Leveraging Machine Learning
by Admin on 04-08-2022 at 1:18 pm

Website GlobalFoundries

About GlobalFoundries:

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit

Summary of Role:

With the current chip shortage, being part of the semiconductor industry as never been so exciting. One of the very first building blocks of creating chips is the Process Design Kit (PDK) and this internship is about having an important impact on how we will build our PDKs in the future. Being the chosen candidate for this project is your chance to influence and improve how we make chips for numerous applications like automotive, mobile devices, high performance computing and IOTs.

We need someone smart, creative and self-motivated that will be excited to leverage their automation and Machine Learning skills to bring our workflow to the next level.

In the mindset of “correct by construction”, they are many opportunities to improve how we build our PDK libraries, including ones using Machine Learning.

Essential Responsibilities Include:

  • Your work will directly apply to our Analog Mixed Signal Design flow.
  • You will learn and get familiar with various aspects of custom design such as:
    • Cadence Virtuosos technology file development and SKILL coding.
    • Development of SKILL PCells, including writing callbacks and netlisting functions for simulators.
    • Developing layout and schematics in the Cadence Design Environment.
    • Automation and running full custom design flow which includes Simulation, DRC, LVS, Parasitic Extraction, Back-annotation and post-layout simulation.

Other Responsibilities:

  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs

Required Qualifications:

  • Basic knowledge of device level layout and simulation
  • Experience using Linux/Unix Environment.
  • Good programming skills and existing experience in Python
  • Experience with Machine Learning
  • Strong communication skills and ability to collaborate across teams to define common project specs
  • Education – Currently Enrolled in a Master’s Degree Program with EECS, EEE, CS or CSE.
  • Experience – 0 to 2 years.
  • Travel – none
  • Language Fluency – English
  • Physical Capacity Demands – None.

Preferred Qualifications:

  • Knowledge of process design kits (PDKs), Cadence Virtuoso and/or Cadence SKILL programming language
  • Good understanding of semiconductor process layout rules and concepts.
  • Experience with Data Science would be a plus.
  • Experience with UX design
Apply for job

To view the job application please visit

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