DFT (Design for Test) Engineer– ASIC

Job responsibilities:

• Has worked on scan-stitching; and has good knowledge of Scan-stitching related concepts.
• Has worked on MBIST implementation and is confident with the Tessent flow of mbist-insertion.
• Has worked on ATPG; and is well-conversed with the files required to run
• ATPG. Knowledge and experience with Tessent ATPG (mentor) is a plus
• Has worked on Spyglass-Lint.
• Knowledge of automation scripts is a plus.
• Knows the basics of JTAG & IJTAG.
• Support Spyglass debug and coverage co-relation.
• Support scan-stitching runs. Debug DRC other scan-related issues
• Support ATPG. debug ATPG issues. debug coverage holes.
• Support MBISTBISR insertion. debug insertion issues verification issues
• Support gate-level simulations.
• Job Types: Full-time, Regular / Permanent