Design Engineer– ME
Website Cadence
- Complete design implementation flows and related QA signoff for Serdes IP: Synthesis, CTS, STA, DFT/ATPG, , LEC/CLP, etc.
- Support design automation to improve Serdes IP quality and efficiency
- EDA flows, environment, and related QA define, develop, maintain, and enhancement.
- Power, speed and area (PPA) optimization.
- Advanced process technology design implementation flows evaluation.
- Support backend team to complete chip implementation signoff and tape out.
- Support chip back performances measurement and correlation.
The Data Crisis is Unfolding – Are We Ready?