The world is transforming – and so is Intel! Here at Intel, we believe the world needs technology that can enrich the lives of every person on Earth. The Advanced Architecture Development Group (AADG) is a CPU Core development team and we believe that developing these technologies takes a team of exceptionally talented individuals who work together to visualize, innovate, and make the future of computing possible.
AADG’s Load/Store Unit and L2 cache RTL team is looking for an experienced engineer with in-depth knowledge of CPU load-store unit design. If you are excited about advanced development of breakthrough technologies for future-generation CPU cores, we invite you to please join us, to do something wonderful!
As a senior member, your responsibilities include, but not limited to:
- Development of architecture and microarchitecture specifications.
- RTL implementation, delivery of high quality logic design that meets functional and PPA goals
- process technology exploration to achieve the highest performance per watt on leading edge process technology
- Work closely with verification team in determining the proper validation strategy for new design and defining and providing feedback on test plans
- Drive design convergence, perform all aspects of the SoC design flow from high level design to synthesis, place and route, timing and power to create a manufacturing-ready design database
Minimum Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related Computing discipline and 8+ years of experience – OR – a Master’s degree in Electrical/Computer Engineering, Computer Science or related Computing discipline and 6+ years of experience – OR – a PhD in Electrical/Computer Engineering, Computer Science or related Computing discipline and 4+ years of High performance CPU design experience:
- Knowledge of coherency protocols, total store ordering, TLB, paging, and cache design are essential.
- Knowledge of CPU architecture, including the concept of Instruction Fetch, Decode, Out of Order execution, Register Renaming, Branch prediction
- Knowledge of Verilog or SystemVerilog
- Understanding of high performance CPU design techniques
- Understanding of power reduction techniques
- Understanding of SoC Physical design flow from high level design to synthesis, place and route, timing and power optimization
- Understanding of trade-off and optimization techniques between Performance, Power and Area
- General scripting and programming skills (Python, Perl, C/C++, etc.)
- Familiarity with functional verification or formal verification is a plus
Apply for job
To view the job application please visit jobs.intel.com.