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IC Design Verification Engineer

IC Design Verification Engineer
by Daniel Nenni on 08-10-2020 at 9:14 pm

Website Cadence

Design Verification engineer who can understand Design specification and develop test/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals.

Must be able to obtain and maintain a Department of Defense classified clearance.

Understand Design specification and develop test/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals.

Strong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. A strong positive attitude and ability to work in a team is a must. Self-motivated and willing take up additional responsibilities to contribute to team’s success.

Desirable skills and experience

Verification skills such as UVM testbench architecture, development and debug
Constraint Randomization
Fundamental SoC Architecture knowledge
Knowledge of UNIX , C/C++, scripting programming languages such as Perl, TCL
Strong verbal and written communication skills in English
Self-motivated and strong teamwork skills

Must be able to obtain and maintain a Department of Defense classified clearance.

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To view the job application please visit cadence.wd1.myworkdayjobs.com.