ASIC Digital Design Engr, Sr I

Job Description and Requirements

Seeking a highly motivated and innovative Digital Verification Engineer with exceptional theoretical and practical background in high-speed data recovery circuits. Working as part of a highly experienced mixed-signal design team, you will be involved in verifying current and next generation products.

The candidate will be involved in verifying current and next generation Backplane Ethernet, PCIe, SATA and USB 2/3, and/or MIPI CPHY/DPHY SERDES products. The position offers an excellent opportunity to work with digital and mixed signal design engineers accountable for delivering high-end mixed-signal designs.

Responsibilities will include:

• Defining and tracking Verification Testplans;
• Designing and writing constrained-random SystemVerilog testbenches using a UVM;
• Writing SystemVerilog assertions;
• Writing functional coverage;
• Debugging RTL and GLS failures;
• Firmware Debug;
• Bug Tracking using Software tools such as Jira;
• Code coverage Analysis;

Requirements:

• Preferred MSEE with at least 5 years of digital design and verification industry experience
• Must have hands-on experience in writing complex testcases in Verilog and System Verilog using UVM

Preferred Experience:

• Knowledgeable on High-speed Digital & Mixed-signal Design
• Knowledgeable on Asynchronous clock crossings