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ASIC Digital Design Engineer

ASIC Digital Design Engineer
by Admin on 06-11-2020 at 3:30 am

Website Synopsys

Synopsys, a world leader in the Semiconductor IP industry, is seeking a Digital Front-End Verification Engineer whose mandate is to:

  • Work in a Digital and Verification Development team contributing to the development and validation of complex digital mix signals for high-speed interface IP.
  • Engage in verification activities under supervision of more experienced personnel, and to exercise judgment to determine appropriate actions to achieve the required specifications.
  • Exposure to mixed signal validations flow. Co-sim.
  • Build productive working relationships, mostly within the team.
  • Participate in applicable product/project reviews.
  • Prepare and present reports outlining the outcome of technical projects.

Key Qualifications

  • University degree in electronics engineering or computer science
  • Deep Knowledge of IC design flows
  • Analog design knowledge
  • Analog tools and spice simulators understanding
  • Willingness to learn new things
  • Good team-player
  • Organizational skills are essential
  • Good problem-solving skills
  • Good English communication skills

Preferred Experience

  • 2+ years of relevant experience is highly preferred
  • Experience in producing high-quality technical documentation is desirable
    Experience in Verilog/VHDL
  • Proficiency in at least on programming language such as Python, C, C++ and MatLab
  • Experience in System Verilog or VMM or OVM or UVM   
  • Exposure to Unix, Perl and TCL scripting
Apply for job

To view the job application please visit sjobs.brassring.com.