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AI Verification Engineer

AI Verification Engineer
by Admin on 04-08-2022 at 11:49 am

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Hardware Verification Engineer (Entry/Senior/Principal)

Verification Engineer involved in functional verification and emulation of Inference SoC and EFLX (embedded FPGA) cores in different process nodes.


  • Responsible for all aspects of verification and emulation.
  • Integration of industry standard Verification IPs
  • Development and debug of UVM/SV testbenches for SoCs and TPU
  • Bring-up and integration verification of cores, NoC, LPDDR4X/5 memory, PCIe, USB, DFT subsystems
  • Development of verification testbench for silicon validation, post-silicon bring-up and checkout; Linux-based validation using C++/Python or similar
  • Development of coverage plans and metrics, drive coverage activities and test writing
  • Gate-Level Simulation/UPF simulation and debug
  • Emulation of SoC and/or TPU using an industry standard emulation tool
  • Silicon On-tester pattern generation using standard IP functional features


  • BSEE/MSEE with at least 5 years of relevant industry experience
  • Must be very smart and very motivated
  • Must have hands-on experience in VIP setup/integration of tools from Synopsys, Avery, SmartDV or similar
  • Must have hands-on experience with UVM/OVM
  • Must have hands-on experience in developing verification plans for SoC or ASIC architectures
  • Must have hands-on, test-writing experience with SIMD, RISCV or ARM ISA, AMBA, JTAG/DFT architectures
  • Must have hands-on functional coverage analysis and assertion implementation experience
  • Must have hands-on experience with standard functional simulators such as NCSIM or Questa

Preferred Experience

  • FPGA debug exposure
  • LPDDR4X/5, PCIe5/USB4 architecture
  • Emulation flow development in Mentor Graphics’ Veloce or equivalent emulation hardware
  • Exposure to Formal Verification techniques
  • Worked with and directed external contractors
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