Getting Started with RISC-V

As I mentioned before, SiFive and RISC-V are trending topics on SemiWiki.com which makes complete sense since we have been covering semiconductor IP and ARM since we first went online in January of 2011.

In total we have published 707 IP related blogs that earned 3,565,140 views (5043 views per blog average). Out of that, 254 are ARM related blogs which earned 1,525,641 views (6,006 average). We also wrote a book on ARM “Mobile Unleashed” that has been downloaded more than 100,000 times so that probably helps as well. Thus far we have done 7 RISC-V related blogs which have earned a whopping 117,666 views (16,806 average).

Bottom line: SemiWiki is the place to read about Semiconductor IP from experts, absolutely!

SiFive is just finishing up a three part series of webinars on RISC-V. In fact the third one is next week so you still have time to watch the first two and register for the third. If you are interested in joining the RISC-V revolution this is a must see series. Even if you are a hard core ARM enthusiast, this series will give you a peek into the future of open-source semiconductor IP.

Getting started with SiFive IP
Three part series introducing Engineers to RISC-V and RISC-V Core IP

Part I: RISC-V 101
This one-hour webinar took place on Sep 12, 2017

This webinar provided an introduction to RISC-V, covering areas such as the Register File, Instruction Types, Modes, Interrupts, and Control and Status Registers. Prior knowledge of RISC-V is not necessary, but having a basic understanding of Computer Architecture would be beneficial.

Hosted by:

Drew Barbier; Field Engineer at SiFive, Inc.
Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.

Krste Asanovic, Chief Architect at SiFive, Inc.
In addition to serving as Chief Architect at SiFive, Krste is a Professor in the EECS dept. at the U. of California, Berkeley, where he also serves as Director of the ASPIRE Lab. Krste leads the RISC-V ISA project at Berkeley, and is Chairman of the RISC-V Foundation. He is an ACM Distinguished Scientist and an IEEE Fellow. Krste Received a PhD from UC Berkeley and a BA from the U. of Cambridge.

Post Webinar Materials

• Full Webinar Recording
• Presentation Slides
• Q&A

Part II: Introduction to SiFive RISC-V Core IP
This one-hour webinar took place on Oct 17, 2017

This webinar focused on Embedded Developers who are interested in learning more about the RISC-V architecture. Part two introduced the SiFive RISC-V Core IP Products; the E31 RISC-V Core IP and the E51 RISC-V Core IP.

Hosted by:

Drew Barbier; Field Engineer at SiFive, Inc.
Drew has worked in the Semiconductor industry for over 10 years in various engineering and customer facing roles. At SiFive Drew is responsible for a variety of tasks including customer support, software and development tools, ecosystem development, documentation, and whatever makes the customer experience great.

Jack Kang; VP of Product and Business Development @Sifive, Inc.
Jack has held a variety of senior business development, management, and product marketing roles at both NVIDIA and Marvell, with a track record of successful, large scale design wins. Jack started his career as a frontend design engineer, focusing on CPU architecture and design. Jack received his BS degree in Electrical Eng. and Computer Science from UC Berkeley.

Post Webinar Materials

• Full Webinar Recording
• Presentation Slides
• Q&A

Part III: Evaluating SiFive RISC-V Core IP

Part 3 of the Getting Started with SiFive IP webinar series will demonstrate how to use the evaluation versions of our the E31 and E51 RISC-V Core IP. In this webinar we will download and program the an Arty FPGA board with one of the evaluation images, and use Freedom Studio to program load and debug a program.

REGISTER HERE

This one-hour webinar will take place on January 17th, 2018.

About SiFive
SiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Andrew Waterman, Yunsup Lee and Krste Asanovic, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in Silicon Valley and has venture backing from Sutter Hill Ventures, Spark Capital and Osage University Partners. For more information, visit www.sifive.com.