Agile Analog at the 2025 Design Automation Conference #26DAC

See Agile Analog at DAC in the EE Times Chiplet Pavilion (Booth 2308, Level 2)

Learn how to enhance security and performance with our customizable analog IP

Agile Analog is delighted to announce that we will be back exhibiting at the Design Automation Conference (DAC). Come join us in the EE Times Chiplet Pavilion (booth 2308) to learn how our innovative, customizable analog IP solutions are addressing the demands of chip design across a vast range of domains.

Visitors will have the opportunity to dive deep into our expanding portfolio of analog IP, covering essential areas including data conversion, power management, IC monitoring, security and always-on IP. We will be explaining how our IP can empower your designs with optimized performance and efficiency, whether you are looking for precision ADCs, efficient LDOs or robust on-chip PVT monitoring capabilities.

Of particular interest is our anti-tamper security IP. In an ever increasingly connected world protecting sensitive data is critical. Our anti-tamper solutions are designed to provide robust, on-chip security against a wide variety of physical and non-physical attacks, including voltage and clock attacks, safeguarding your devices from malicious intrusions. We will be discussing how our anti-tamper IP can seamlessly integrate with existing Root of Trust (RoT) solutions, enhancing their capabilities to help you meet the latest security standards. This integration offers formidable protection, with a multi-layered approach to chip security that is both flexible and powerful.

What truly sets Agile Analog apart is our groundbreaking Composa™ technology. Composa enables us to automatically generate and customize our analog IP for any process node from any foundry. We have proven this methodology across our IP portfolio on nodes from 180nm to 3nm. This means that we can quickly deliver highly optimized IP that precisely matches your exact specifications, whilst ensuring the best possible Power, Performance and Area (PPA) for your application. No more porting or costly and time-consuming analog re-engineering when moving to a new process or foundry. This unparalleled flexibility extends to our anti-tamper IP as well, allowing for tailored security solutions, delivered fast, regardless of your chosen process node.

We invite attendees to stop by to see us in the EE Times Chiplet Pavilion (booth 2308) at DAC. Our experts will be on hand to discuss your specific design challenges and demonstrate how Agile Analog’s customizable multi-process IP, especially our advanced anti-tamper solutions, can help you achieve your design goals and stay ahead in a competitive landscape. We look forward to seeing you there!

To arrange a meeting to talk with the Agile Analog team at DAC please email info@agileanalog.com

Find out more about Agile Analog at www.agileanalog.com

DAC registration is open.

Also Read:

CEO Interview with Krishna Anne of Agile Analog

Overcoming obstacles with mixed-signal and analog design integration

Podcast EP241: A Look at Agile Analog IP with Chris Morrison