Achieving Extreme Low Power with Synopsys Foundation IP Memory Compilers and Logic Libraries

The relentless demand for lower power SoCs is evident across many markets.  Examples include cutting-edge mobile, IoT, and wearable devices along with the high compute demands for AI and 5G/6G communications. Drivers for low power include battery life, thermal management and, for high compute applications, the overall cost of operation.  Several approaches are available to achieve low power. A common thread for many is the need for optimal Foundation IP, that is, embedded memories and logic libraries. This is an area of significant investment and market leadership for Synopsys. Two informative publications are now available to help you understand the options and benefits that are available.  It turns out achieving extreme low power with Synopsys Foundation IP memory compilers and logic libraries is within reach.

Let’s look at the information that is available.

Technical Bulletin

I’ll start with Optimizing PPA for HPC & AI Applications with Synopsys Foundation IP, a technical bulletin that focuses on logic libraries. The piece provides details on Synopsys’ tool-aware Foundation IP solution. Topics such as optimized circuitry, broad operating voltage range support and the flexibility to add customer-specific optimizations are discussed. The article also offers a perspective on achieving either maximum possible performance or the best power-performance trade-off. The figure below summarizes the logic library circuits available in the HPC Design Kit.

Details of how power improvements are achieved is provided across many applications and design strategies. Topics that are covered include dynamic voltage scaling across a wide operating voltage range, optimizing AI and application-specific accelerator block PPA, solutions for network on chip, and how the Synopsys HPC Design Kit is co-optimized with Synopsys EDA for efficient SoC Implementation.

This technical bulletin provides a rich set of information and examples. You can access this information here.

White Paper

Also available is a comprehensive white paper entitled, How Low Can You Go? Pushing the Limits of Transistors. This piece digs into both embedded memories and logic libraries. It examines the details behind achieving extreme low power. Several application areas are discussed, including mobile, Bluetooth and IoT, high-performance computing, automotive, and crypto.

For embedded memories, several approaches are discussed, including assist techniques and splitting supply voltages. It is pointed out that careful co-optimization between technology and the design of memory assist circuits is required to deliver dense, low-power memory operation at low voltages. Several enhanced assist techniques are reviewed. Improvements in power range from 10% to 37%.

Reliability of memories is also discussed.  The piece explains that as the voltage is reduced, the SRAM cell starts showing degradation. This degradation can cause multiple issues: reads are upset, the bitcell does not flip, SER is pronounced, sensing fails, control signals deviate, and the BL signal weakens. Therefore, assist techniques are needed to support the lower extreme low voltages required by cutting-edge low power applications.

The approaches Synopsys takes here make a significant difference. Strategies to improve reliability and methods to simulate aging are discussed. You should read the details for yourself – a link is coming. The data shows compelling results, with five to ten years of life added.

Logic libraries are also discussed, with strategies to enable deep low voltage operation at 0.4v and below. Architectural optimization is also reviewed. Standard cell architectural techniques can be employed to reduce both dynamic and leakage power. For example, Synopsys uses stack-based versus stage-based architectural techniques for the optimal topology for deep low voltage operation. The strategy behind this approach is presented.

Characterization optimization is also covered. One important piece of characterization is modeling process variation across an SoC, referred to as on chip variation (OCV). Several advanced techniques are employed here, including machine learning to increase accuracy and optimize performance and power.

The white paper concludes with an overview of how to put everything together at the SoC level to achieve deep low voltage operation. Voltage reduction is discussed, along with dynamic voltage and frequency scaling (DVFS) techniques and various shut-down strategies such as light sleep, deep sleep, full shut down and POFF (Periphery OFF) modes.

This white paper covers a number of power optimization topics in excellent detail. I highly recommend it. You can get your copy here.  And that’s how achieving extreme low power with Synopsys Foundation IP memory compilers and logic libraries is within reach.

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