Writing SDC constraints for Asynchronous clocks

[krishh9]

Hello All,

I am new to SDC constraints,
in synchronous clock definition
If A is input port and B is output pin then we can define create_clock on A and generated_clock on B with divide_by option.

Now say X is input and Y is output, and both are asynchronous with each other.
Where such scenario will come in design and how to write SDC constraints on input and output?

Thanks in advance

 

[Bernard Murphy]

Check out create_clock_groups