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What is the 40nm low-leakge process used in this chip ?

I

ippisl

Guest
Here[1],in the presentation by freescale, they say 40nm offers "3x less leakage than 90nm" , but when i look for example at [2] at tsmc offerings, 40nm has 100x higher ioff per um.

Does anybody know how do they achieve this ?


[1]http://www.freescale.com/files/training/doc/dwf/DWF13_APF_IND_T0847.pdf

[2]http://www.europractice-ic.com/technologies_TSMC.php?tech_id=40nm
 
To start with, Freescale has their own fab so they can simply measure leakage at both 90 nm and 40 nm, then summarize the results.

I would think that TSMC made similar leakage reductions moving from 90 nm to 45 nm.

Dielectric materials and purity contribute to leakage characteristics.

The process development people would have the exact answer to how the lower leakage values were achieved, but likely don't want to share their industrial secrets with the world.
 
Daniel,
In the link i gave , there's the TSMC leakage numbers, and their got really bad after 90nm, a phenomena known through the industry. That's why i am asking.

And as far as i know freescale doesn't have a 40nm fab. The most advanced they've got , according to wikipedia is 90nm.
 
My humble guess blow:
This is the backward benefit from the advance node development. Europepractice shows 40nm is a poly gate process. However high k, metal gate certainly can control the gate better. So migrating advanced HKMG to 40nm could be part of the magics you have shown here.
Static leakage is 3x less than 90nm
Enables more integration for a given power envelope.

So to be precise, it is not exactly the same as total leakage reduction...
Freescale should have done a lot contribution also.
 
The table you are reffering to only list one transistor type. The 40nm number is coming from a transistir with a Vt of 0.23V (likely LVT) and has a max off current of 300nA. The 90nm LP transistor listed has a Vt of 0.47V and has an off current of 3nA. I beleive these are the numbers you quote as 100x increase in off current.

You need to get the full device menu and compare the range of Vt available in each technnology. I bet the 40nm node also has a higher Vt options, with leakage in nA/um range. Even higher Vts might be offered, it's just a matter of adding masks for higher Vt.

If a 40nm technology simply offeres the same 3nA/um, your circuit will have at least 2X less leakage compared to 90nm impelemntation just because device width will be at least 2X less. There is no magic.
 
Thanks khaki.

Do you know where i can get the full device menu, on the net ? or is it only under NDA ?
 
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