What is really going on with Intel’s 18a process?

[nghanayem]

Intel is in deep trouble, the 18a process is broken, and it is all down hill from here, right? SemiAccurate dug deeply into the 18a rumors for the last 3+ weeks and hunted them all down.

As you may recall, SemiAccurate was the first, and for years only site that was screaming about Intel’s 10nm problems, with data. Only after it became undeniable did other climb on board. SemiAccurate also called Intel’s potential for outright failure in 2019, again long before anyone else did. We have a long track record of calling Intel’s problems and their successes because we do the groundwork and research rather than parroting back random idiots on the net.

What is really going on with Intel’s 18a process?

Intel is in deep trouble, the 18a process is broken, and it is all down hill from here, right?

www.semiaccurate.com

Be it positive or negative, no matter what SA is saying you can safely assume that he has no inside information to back up his claims. Anyone remember intel 10nm was canceled and would never be capable of reaching high yields so intel skipping ahead to 7nm. From a quick google search this seems to be the first of many claims that 10nm was canceled.

Intel kills off the 10nm process

SemiAccurate has learned that Intel just pulled the plug on their woeful 10nm process.

www.semiaccurate.com

"Now we are hearing from trusted moles that the process is indeed dead and that is a good thing for Intel, if they had continued along their current path the disaster would have been untenable. Our moles are saying the deed has finally been done."

Vaulting an impossibly high bar is fine in theory but in practice it can really hurt, especially if everyone is betting that you will clear it.

Nobody has ever bet intel could clear it. Even if you look back at the semiwiki comments from intel accelerated people were calling it "an aspirational goal that intel should be proud if they even hit half of their goals.". As a college junior at the time I remember thinking something to the tune of "Yeah right! Show me 10nm desktop CPUs before you start talking about 2nm GAA and BSPDNs! Why would a company that can't even project out 2 years be able to see 4 years out.".

If I had to guess, purely based on historical pattern matching, my money would be on PowerVia being the troublemaker.

Your intuition has failed you.

It's not just that "it's getting harder for everyone", it's also "who has better competence to handle this environment".
TSMC has a long history of
(a) cautiously rolling out one improvement at a time. With a plan-B (eg N3B vs N3E) lined up if required.

So what intel has started doing post the cascade of failures during the 2010s? For public examples intel 4+powerVia, pattern shaping, low-NA and high-NA in parallel, and intel claiming back in the late 2010s that 7nm had SAPQ and EUV versions.

(b) not saying anything publicly until the details are worked out and everything is ready.
This means they mostly deliver what they promise, both to customers and to Wall Street.

When you are that behind and starting up a foundry you need to call a shot to build credibility. Calling a four year roadmap publicly puts pressure on delivering and if 18A products launch in a healthy state in 2025 then intel has proven without a shadow of a doubt they can slug it out with TSMC. Moving forward take a look at 14A and 10A intel has not claimed anything concrete about them other than 2yr offsets post 18A and only after others started talking about their 2027 process technology and public angst about what comes next and high-NA rollout plans.

I'm a gonna build my own GAA. And my own BSPD. And I'm gonna do it in two years, in the same product because I'm just that good.

They said they would do that in 4 years from Jul'21 not 2 years after Jul'21. And if they do deliver 18A products in 2025, then I guess they are "just that good".

And five years from now I'm gonna be delivering CFETs.

They have never claimed that.

And eight years from now I'm gonna shipping graphene chips.

Or this. In fact intel doesn't even talk about graphene 2D channels. Industry is moving to TMDs.

 

[MKWVentures]

Given all the wild speculation, I would even more recommend just looking at what is actually happening

1) Intel decided not to ramp 20A and moved the current Arrow lake skus to TSMC N3. whatever the cause, this is a huge unexpected (by investors) change.
2) Intel plans to have 18A products by June 2025 launched and selling to the public.
3) Intel external wafer foundry is expected to have meaningful revenue in 2027, not 2025, not 2026.
4) the first external 18A customer will tape out its part in 2025 (this lines up with #3
5) Intel is ramping TSMC wafer starts

For the next two quarters, focus on actual revenue, actual margins for foundry and product Co.
Focus on the changes to Intels business and ramp model that will be announced over the next 2 months

In 2025, Intel cannot fill even half a normal fab with 18A based on expected loadings. So there needs to be major increases and roadmap announcements by June of 2025 to make 18A a ramp-able process. Technology doesnt matter if you dont have a business model to ramp it and be cost competitive with TSMC.

IMO the issue is the same thing as in 2020. The numbers do not support Intel doing manufacturing and development internally without a large, cost effective foundry business.

 

[MKWVentures]

There are two problems with 18A, the extremely high expectations Intel set and the PDK.

I am close to the ecosystem and the ecosystem does not lie. The PPA of 18A is in serious question. It is fun to quote numbers based on SRAM and other test structures but when you try and design a complex SoC or a big fat AI chip the power, performance and area numbers come up differently. Power is an especially tricky one. TSMC on the other hand is an expert at setting customers expectations and low power is their specialty. How many years has TSMC been manufacturing mobile SoCs?

In regards to yield, if you compare TSMC yield to Intel yield, Intel has ALWAYS had a yield problem. The same with Samsung, even more so of late.

Bottom line: The ONLY solution to Intel's manufacturing problems is to stop comparing them to TSMC. It really is a different animal: Pure-Play foundry versus an IDM foundry. Comparing TSMC to Intel is like comparing SemiWiki to Semiaccurate.

Question: Why is Intel not ramping foundry on 22nm, 14, 7nm, 3nm? Why can't they compete with Grace, UMC, SMIC, GF after 3 years? shouldnt they be able to sell at least 10K wafers per month across all nodes?

 

[osnium]

Question: Why is Intel not ramping foundry on 22nm, 14, 7nm, 3nm? Why can't they compete with Grace, UMC, SMIC, GF after 3 years? shouldnt they be able to sell at least 10K wafers per month across all nodes?

They are developing a foundry compatable 12 nm node with UMC, which will ramp in Arizona.

Intel and UMC Announce New Foundry Collaboration

The companies will develop a 12-nanometer process platform to be manufactured at fabs in Arizona.

www.intel.com

 

[kevin01]

Question: Why is Intel not ramping foundry on 22nm, 14, 7nm, 3nm? Why can't they compete with Grace, UMC, SMIC, GF after 3 years? shouldnt they be able to sell at least 10K wafers per month across all nodes?

Their foundry use intel specific tools including eda, so these mature processes cannot be easily utilized by others.

+1 for "They are developing a foundry compatable 12 nm node with UMC, which will ramp in Arizona."

 

[kevin01]

Given all the wild speculation, I would even more recommend just looking at what is actually happening

1) Intel decided not to ramp 20A and moved the current Arrow lake skus to TSMC N3. whatever the cause, this is a huge unexpected (by investors) change.
2) Intel plans to have 18A products by June 2025 launched and selling to the public.
3) Intel external wafer foundry is expected to have meaningful revenue in 2027, not 2025, not 2026.
4) the first external 18A customer will tape out its part in 2025 (this lines up with #3
5) Intel is ramping TSMC wafer starts

I started to follow Intel closely since mid 2023. All the above 5 things, including 1), were not news to me. To make 5) more specific, 30% of Intel products wafers are from TSMC today.

For the next two quarters, focus on actual revenue, actual margins for foundry and product Co.
Focus on the changes to Intels business and ramp model that will be announced over the next 2 months

In 2025, Intel cannot fill even half a normal fab with 18A based on expected loadings. So there needs to be major increases and roadmap announcements by June of 2025 to make 18A a ramp-able process. Technology doesnt matter if you dont have a business model to ramp it and be cost competitive with TSMC.

What you described is largely true here. According to Intel, in terms of revenue, 2025 will be mostly about Intel 3, and a bit of 18A. 2026 will be the year 18A starts to really ramp to major volume and revenue.

IMO the issue is the same thing as in 2020. The numbers do not support Intel doing manufacturing and development internally without a large, cost effective foundry business.

I strongly disagree here. In 2020, IFS did not even know how to effectively use EUV, now they are mastering 18A, arguably the most advanced leading edge process.

Technology leadership first, $$s will follow. The way I see it, Intel has high volume products which are crying to use the most advanced manufacturing technology. It is not that 18A cannot find the internal demand (or external demand, for that matter), it is that 18A needs to be really good (including PPA and cost) compared to competitions.

It is kind of laughable that Intel competitors won't use IFS. If IFS offers the best tech, and your competitors are using it to outrun you, you will be FORCED to use it, too.

Again, Technology leadership first, $$s will follow.

 

[DougDD]

+1 to what siliconbruh999 said.

A Clearwater Forest chip consists of 14 small chiplets, so it should yield quite well (probably even better than PTL) on the wafer level. However, the challenge is to do 3D chip stacking of so many chiplets.

A few weeks ago, IFS head said PTL yielded well, but did not use the same language for CWF. My speculation is that their 3d stacking technology was the bottleneck.

This is what Intel said:

<<How It Works: In successfully booting operating systems without additional configurations or modifications, both Panther Lake and Clearwater Forest are clearly indicating
the health of Intel 18A — the company’s leading-edge process technology that is expected to return Intel to process leadership in 2025. Other signs of health include Panther
Lake DDR memory performance already running at target frequency. Next year's Clearwater Forest, the archetype of future CPU and AI chips, will mark the industry's first
mass-produced, high-performance solution combining RibbonFET, PowerVia, and Foveros Direct 3D for higher density and power handling. Clearwater Forest is also the
lead product for the Intel 3-T base-die technology. Leveraging Intel Foundry’s systems foundry approach, both products are expected to deliver significant improvements
in performance per watt, transistor density and cell utilization.>>

https://www.intel.com/content/www/u...ndry-achieves-major-milestones.html#gs.eyi4tl

 

[DougDD]

Their foundry use intel specific tools including eda, so these mature processes cannot be easily utilized by others.

+1 for "They are developing a foundry compatable 12 nm node with UMC, which will ramp in Arizona."

Cadence and Synopsys are becoming encouraged by what Intel is doing:

<<How Customers are Involved: In gaining access to the Intel 18A PDK 1.0 last month, the company’s EDA and IP partners are updating their tools and design flows to
enable external foundry customers to begin their Intel 18A chip designs. This is a critical enabling milestone for Intel’s foundry business.

“Cadence’s strategic collaboration with Intel Foundry helps accelerate our mutual customers’ innovation by providing access to industry-leading EDA solutions and IP optimized
for Intel 18A,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “It is very encouraging to see Intel 18A achieve this critical
milestone, and we are pleased to support customers on their leading-edge designs on 18A.”

Shankar Krishnamoorthy, general manager of the EDA Group at Synopsys, said, “It’s great to see Intel Foundry hitting these critical milestones. With 18A now customer-ready,
Intel Foundry is bringing together the necessary components needed to design next-generation AI solutions that our mutual customers require and expect. Synopsys plays a
mission-critical role as an on-ramp to the world’s foundries, and we are proud to work with Intel Foundry to enable Synopsys’ leading EDA and IP solutions for their leading-edge process.”>>

https://www.intel.com/content/www/u...ndry-achieves-major-milestones.html#gs.eyi4tl

 

[osnium]

I started to follow Intel closely since mid 2023. All the above 5 things, including 1), were not news to me. To make 5) more specific, 30% of Intel products wafers are from TSMC today.


What you described is largely true here. According to Intel, in terms of revenue, 2025 will be mostly about Intel 3, and a bit of 18A. 2026 will be the year 18A starts to really ramp to major volume and revenue.


I strongly disagree here. In 2020, IFS did not even know how to effectively use EUV, now they are mastering 18A, arguably the most advanced leading edge process.

Technology leadership first, $$s will follow. The way I see it, Intel has high volume products which are crying to use the most advanced manufacturing technology. It is not that 18A cannot find the internal demand (or external demand, for that matter), it is that 18A needs to be really good (including PPA and cost) compared to competitions.

It is kind of laughable that Intel competitors won't use IFS. If IFS offers the best tech, and your competitors are using it to outrun you, you will be FORCED to use it, too.

Again, Technology leadership first, $$s will follow.

It’s just really hard to get technology leadership when going against a long established leader like TSMC that has more money and engineers who are as good or most likely better.

 

[Maximus]

It’s just really hard to get technology leadership when going against a long established leader like TSMC that has more money and engineers who are as good or most likely better.

TSMC only emerged as the technology leader with the launch of N7 in 2018.
Intel employee number: 125000 --> 110000 (after layoff) tsmc employee number: ~80000
It's unclear how many Intel employees are involved in manufacturing, but it's doubtful that TSMC holds an advantage in terms of engineer headcount.

 

[bashee_wang]

Well said. Intel's own presentation matches what you described.

1. Intel admitted that it would not compare favorably in terms of power against TSMC processes until 14A (which has a tremendous amount of uncertainty). This is indeed a big disadvantage, since much of industry (even HPC customers such as NVDA and AMD) emphasizes lowering power usage.

2. It only announced two internal products based on 18A so far, one is Panther Lake, another is Clearwater Forest. PTL's largest compute tile is only 1.2 cm^2, and CWF's compute tiles are even smaller. This is not an accident, because big fat chips requires much higher yields. It remains to be seen when IFS can improve their yields from D0 of 0.4 to 0.2, or even 0.1.

I can see several positives:

1. Intel 3 seems to be doing well, producing large chips such as Granite Rapids on time. And the yield improvement from Intel 4 seems to be significant, as Intel 4 was only used to produce very small MTL compute tiles (~0.4 cm^2 die size).

2. From a technical point of view, the current management and IFS team seems to have learned their lessons in late 2010s, largely hitting their goals.

3. IFS does not need large amount of external customers to sustain itself financially for a while. In the next 2-3 years, they just need a few external customers to help prove that its PDK, its tools, and its service level are good enough; but these customers does not need to be whales.

4. TSMC seems to be also slowing (N5 -> N3E takes about 3 years). The improvements are harder and harder to come by in general.

View attachment 2257

Based on this chart, can we say that Intel can be considered to have one of the most advanced package assembly technologies globally?

 

[tooLongInEDA]

Cadence and Synopsys are becoming encouraged by what Intel is doing:

<<How Customers are Involved: In gaining access to the Intel 18A PDK 1.0 last month, the company’s EDA and IP partners are updating their tools and design flows to
enable external foundry customers to begin their Intel 18A chip designs. This is a critical enabling milestone for Intel’s foundry business.

“Cadence’s strategic collaboration with Intel Foundry helps accelerate our mutual customers’ innovation by providing access to industry-leading EDA solutions and IP optimized
for Intel 18A,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “It is very encouraging to see Intel 18A achieve this critical
milestone, and we are pleased to support customers on their leading-edge designs on 18A.”

Shankar Krishnamoorthy, general manager of the EDA Group at Synopsys, said, “It’s great to see Intel Foundry hitting these critical milestones. With 18A now customer-ready,
Intel Foundry is bringing together the necessary components needed to design next-generation AI solutions that our mutual customers require and expect. Synopsys plays a
mission-critical role as an on-ramp to the world’s foundries, and we are proud to work with Intel Foundry to enable Synopsys’ leading EDA and IP solutions for their leading-edge process.”>>

https://www.intel.com/content/www/u...ndry-achieves-major-milestones.html#gs.eyi4tl

Of course Cadence and Synopys are backing every [viable] horse in the foundry race. Not least since Intel are paying them significant amounts to do this enablement work. And this sort of development work increases their EDA licence usage (and revenues) whether it results in production silicon or not. Provided they have the engineering resources to support this (Intel), they'd be mad not to.

 

[siliconbruh999]

Of course Cadence and Synopys are backing every [viable] horse in the foundry race. Not least since Intel are paying them significant amounts to do this enablement work. And this sort of development work increases their EDA licence usage (and revenues) whether it results in production silicon or not. Provided they have the engineering resources to support this (Intel), they'd be mad not to.

Intel is also their biggest customer so they won't say no to some promotion for their customer

 

[Joseph Byrne]

Question: Why is Intel not ramping foundry on 22nm, 14, 7nm, 3nm? Why can't they compete with Grace, UMC, SMIC, GF after 3 years? shouldnt they be able to sell at least 10K wafers per month across all nodes?

The have a 22nm foundry process from the previous time they said they were going to offer contract manufacturing.

 

[delong.height]

Tsmc today has ~10x value of Intc. Who has the better competence to handle the situation? The answer is quite obvious, as the resources available to them are vastly different. Tsmc can afford several teams devolping various strategies at the same time to hedge, while Intel does not even have money to finish new site construction. Does that mean Intel does not stand a chance, and just need to pack and go home? No.

Intel still has great talent, (limited) resources, and technical know-hows. I am rooting for Intel's resurgence.

Btw, if someone is winning, it seems that whatever it is planning to do is right; while a loser seems to do everything wrong. This is just human perception psychology.

I blamed the cost of building in the US. If Intel has the same low cost manufacturing advantage PLUS government subsidy. It will be able to do the same as what TSMC has done.

Pat Gelsinger just chose the wrong strategy. Chips doesn't have to be build in the US because there're military bases all over the world! Why you need it specfically in the US when you are getting free protection, say in Africa, South-east Asia, Japan, Korea, Taiwan?

 

[delong.height]

It is kind of laughable that Intel competitors won't use IFS. If IFS offers the best tech, and your competitors are using it to outrun you, you will be FORCED to use it, too.

That is the argument I always make

 

[MKWVentures]

Kevin01 Said: "It is kind of laughable that Intel competitors won't use IFS. If IFS offers the best tech, and your competitors are using it to outrun you, you will be FORCED to use it, too."

That is the argument I always make

If Intel is best, Of course people will use them. The question is whether Intel has the best tech and foundry services (delivery/price/PDK).

Perhaps we should wait to see how Intel is delivering actual products and processes before assuming Intel has leadership.

IBM announced leading 2nm GAA product in 2021 so perhaps IBM and Rapidus are the true leaders?

Lets see what happens.

 

[tooLongInEDA]

That is the argument I always make

You can make exactly the same argument in reverse.

If you were the current combined (design + fabs) Intel and had the best tech, why would you offer it to competitors of Intel (design) [on the same terms, costs and schedules] ?

Equally, how much better would Intel foundry need to be vs TSMC for it to be worth the additional risk of working with a competitor ?

I suggest the cost of switching from TSMC to IFS is significantly higher than simply having slightly better tech. To adapt what they used to say about IBM, no ones going to get fired for buying from TSMC.

 

[MKWVentures]

It’s just really hard to get technology leadership when going against a long established leader like TSMC that has more money and engineers who are as good or most likely better.

We have been through this before: Intel spends more money than TSMC and has more people in R&D. they spend more on development. Intel does not spend too little

 

[Daniel Nenni]

We have been through this before: Intel spends more money than TSMC and has more people in R&D. they spend more on development. Intel does not spend too little

Intel does spend more money directly than TSMC but the ecosystem spends a huge amount of money that TSMC leverages. IP development is an easy example but there are many more like R&D partnerships. How many companies have R&D teams in Hsinchu to work closely with TSMC? This is the problem I have been speaking of. A comparison between Intel and TSMC is not calculable and R&D spending is another clear example. The TSMC ecosystem has been spending billions of collective dollars a year for 30+ years that TSMC has directly benefitted from. So many companies around the world have internal dedicated TSMC support staff that TSMC does not pay for. All told, TSMC probably has a million people working for them, my opinion.

Stop by the TSMC Open Innovative Platform Conference this month and you will see the direct benefits of the TSMC ecosystem R&D support.

https://www.tsmc.com/static/english/campaign/oip2024/index.html