Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/what-is-really-going-on-with-intel%E2%80%99s-18a-process.20944/page-4
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

What is really going on with Intel’s 18a process?

I suspect LNL and ARL primarily in N3 was a decision made much earlier than Jun 2023. It was claimed by various sources that Bob Swan pre-purhcased TSMC capacity.

They did intend to build low sku of ARL in 20A, but changed their mind to save money. They even stopped free employee coffee to save money, which honestly did not save much money, so I can totoally understand why they stopped 20A here, even though it wad a bad look.

I don't think there is any credibility issue here, as 20A was never communicated for external uses.

To be a trusted friend, people watch me not only on what I do in the office but also what I do to my spouse, my kids and my dog. Especially when there is money involved.
 
I suspect LNL and ARL primarily in N3 was a decision made much earlier than Jun 2023. It was claimed by various sources that Bob Swan pre-purhcased TSMC capacity.

They did intend to build low sku of ARL in 20A, but changed their mind to save money. They even stopped free employee coffee to save money, which honestly did not save much money, so I can totoally understand why they stopped 20A here, even though it wad a bad look.

I don't think there is any credibility issue here, as 20A was never communicated for external uses.

Intel 4 and Intel 20A was chiplet only for Internal Intel design, no IOs etc for full chip wafer manufacturing. They were barely half nodes much less full nodes. 3 nodes in 5 years is good but PG had to go big with 5 nodes and lost confidence all the way around. :ROFLMAO:
 
Intel 4 and Intel 20A was chiplet only for Internal Intel design, no IOs etc for full chip wafer manufacturing. They were barely half nodes much less full nodes. 3 nodes in 5 years is good but PG had to go big with 5 nodes and lost confidence all the way around. :ROFLMAO:
I often wonder why there was no oversight from the board on Pat, oh yeah nobody on the board has a clue 🤣😂
 
Intel 4 was chiplet only for Internal Intel design, no IOs etc for full chip wafer manufacturing.
1726428760650.png

Incorrect Dan. Intel 4 does have IOs. Even if you want to ignore the high speed D2D connections on MTL cpu die, FIVIR, PLLs, etc. The edge version of Xeon 6 has full ethernet and PCIE interfaces on an i4 IO die. Heck if you look at older intel roadmaps large die Xeon 6 was listed as intel 4 not intel 3. In addition to the intel 4 5G base station intel talked about last year, it is obvious that only the MTL CPU being on intel 4 was a conscious design choice from CCG rather than a technological limitation of intel 4 not being a "real" process technology.
They were barely half nodes much less full nodes.
Intel 4 240h HP cell vs the intel 7 HD cell was a similar shrink to N3 HD over N5 HD, and a larger perf/watt improvement than N5 vs N7. To call intel 4 a half node step over intel 7 is at best disengous. Intel 20A was also GAA and BSPD, so clearly a very different node than intel 3. Now if you want to call intel 3 and 18A "half nodes", sure no disagreements there. But saying an intel process technology isn't real because it only runs internal chiplets (something that 100% of even intel's TSMC products have) would be like me saying original N3 was never a real node because only Apple SOCs and intel SOCs have/will ever be built on it and because there is no RF capability on any N3 or N3E products to date. If I said something incorrect like that I would rightfully be called out.
3 nodes in 5 years is good but PG had to go big with 5 nodes and lost confidence all the way around.
Using intel's metrics TSMC did 3N4Y and Samsung did 3N4Y. But if we want to call 5N4Y actually 3N4Y or 2N4Y, then we are talking TSMC "only" doing 1N4Y and Samsung "only" doing 2N4Y in the same time period under scrutiny. If we are going to apply some set of criteria to one firm it needs to be applied to them all.
 
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I suspect LNL and ARL primarily in N3 was a decision made much earlier than Jun 2023. It was claimed by various sources that Bob Swan pre-purhcased TSMC capacity.

They did intend to build low sku of ARL in 20A, but changed their mind to save money. They even stopped free employee coffee to save money, which honestly did not save much money, so I can totoally understand why they stopped 20A here, even though it wad a bad look.

I don't think there is any credibility issue here, as 20A was never communicated for external uses.
I agree. Everyone following this knows that Intel cancelled 20A that was originally meant for
their internal Arrow Lake. But, at the same time, Intel reminds everyone how well 18A is doing -
which is meant for both outside customers as well as Intel internally. Intel definitely needs to
save money and they clearly said that they've put all of their 20A learnings into 18A here:

https://www.intel.com/content/www/us/en/newsroom/opinion/continued-momentum-intel-18a.html#gs.envgxt

Also, one thing that I haven't seen anyone discuss is that the reported defect density of 18A being below 0.4
is a composite D0 - so it's for the transistors and backside power. How do we know? Listen to Pat @ 20
minutes here:

https://www.intc.com/news-events/ir...829-deutsche-banks-2024-technology-conference
 
This whole 4N5Y seems to be some showmanship, same with the node number designation.

Maybe we need a Semiwiki panel to approve technology claims as even IEDM and VLSI have sunken to new lows and more marketing than reality
It is mostly showmanship and a nice slogan, not a rigorous technical claim. 5N4Y sounds better and more memorable than 3N4Y or 3N5Y.
 
View attachment 2289
Incorrect Dan. Intel 4 does have IOs. Even if you want to ignore the high speed D2D connections on MTL cpu die, FIVIR, PLLs, etc. The edge version of Xeon 6 has full ethernet and PCIE interfaces on an i4 IO die. Heck if you look at older intel roadmaps large die Xeon 6 was listed as intel 4 not intel 3. In addition to the intel 4 5G base station intel talked about last year, it is obvious that only the MTL CPU being on intel 4 was a conscious design choice from CCG rather than a technological limitation of intel 4 not being a "real" process technology.

Intel 4 240h HP cell was a bigger shrink vs even the intel 7 HD cell was a similar shrink to N3 HD over N5 HD, and a larger perf/watt improvement than N5 vs N7. To call intel 4 a half node step over intel 7 is at best disengous. Intel 20A was also GAA and BSPD, so clearly a very different node than intel 3. Now if you want to call intel 3 and 18A "half nodes", sure no disagreements there. Saying an intel process technology isn't real because it only runs internal chiplets (something that 100% of even intel's TSMC products have) would be like me saying original N3 was never a real node because only Apple SOCs and intel SOCs have/will ever be built on it and because there is no RF capability on any N3 or N3E products to date. I would rightfully be called out if I said something incorrect like that.

Using intel's metrics TSMC did 3N4Y and Samsung did 3N4Y. But if we want to call 5N4Y actually 3N4Y or 2N4Y, then we are talking TSMC "only" doing 1N4Y and Samsung "only" doing 2N4Y in the same time period under scrutiny. If we are going to apply some set of criteria to one firm it needs to be applied to them all.

I was talking about I/O support for a complex SoC type of chip not a chiplet but I could certainly be miss informed. Did Intel actually make a full chip at 4 or 20A? Or is it just theoretically possible that they could?

At a minimum PG was disingenuous about 5N4Y. Intel 7 took years to make it into HVM, nothing to brag about at all. Intel 3/4 is one node and Intel 20/18A is another node. If you talk about development time it took Intel 8 years to do 3 nodes? If you are talking about just releasing nodes Intel released 3 nodes in 4 years and only one of those is in HVM at the full chip level, right?

TSMC made no such claim, they know better than that, so why even mention it? My criteria here is honesty and PG failed on this one.

The problem with PR BS like this is that it sets expectations incorrectly, which is what PG is paying for now. PG and whoever else owns Intel stock. Other CEOs have been fired for less, including the two previous Intel CEOs.
 
This whole 4N5Y seems to be some showmanship, same with the node number designation.

Maybe we need a Semiwiki panel to approve technology claims as even IEDM and VLSI have sunken to new lows and more marketing than reality

The good news is that conference attendance is very good this year. The bad news is that conference papers/sessions are more marketing than previous years. I’m not sure what the correlation is.
 
I was talking about I/O support for a complex SoC type of chip not a chiplet but I could certainly be miss informed. Did Intel actually make a full chip at 4 or 20A? Or is it just theoretically possible that they could?

At a minimum PG was disingenuous about 5N4Y. Intel 7 took years to make it into HVM, nothing to brag about at all. Intel 3/4 is one node and Intel 20/18A is another node. If you talk about development time it took Intel 8 years to do 3 nodes? If you are talking about just releasing nodes Intel released 3 nodes in 4 years and only one of those is in HVM at the full chip level, right?

TSMC made no such claim, they know better than that, so why even mention it? My criteria here is honesty and PG failed on this one.

The problem with PR BS like this is that it sets expectations incorrectly, which is what PG is paying for now. PG and whoever else owns Intel stock. Other CEOs have been fired for less, including the two previous Intel CEOs.
I think it is PG/his strategy hostages all stakeholders. I agree with you that given the performance, he should step down.
 
To be a trusted friend, people watch me not only on what I do in the office but also what I do to my spouse, my kids and my dog. Especially when there is money involved.

What I'm trying to say is that Intel needs to convince potential Intel Foundry customers:

Please trust us. While we may cancel, change, or postpone our roadmap for internal projects, we won't do the same for external customers. Even if a cancellation could save Intel $500 million, we won't let that happen to affect your projects.
 
I think it is PG/his strategy hostages all stakeholders. I agree with you that given the performance, he should step down.
I can hardly believe anybody else (other than Pat Gelsinger) could do a better job in terms of returning to foundry leadership in a few short years. Samsung foundry is in deep trouble now, to the point that both TSMC and IFS don't care about them; TSMC also spent 3 good years to develope a successful 3nm node (N3E).

What Pat Gelsinger and Intel management did not anticipate was a few years of bad PC business since covid-19 and sudden AI investment boom.

In the past few years, one thing I learned is that everything takes a long time in the semiconductor business. Just be patient.
 
I can hardly believe anybody else (other than Pat Gelsinger) could do a better job in terms of returning to foundry leadership in a few short years. Samsung foundry is in deep trouble now, to the point that both TSMC and IFS don't care about them; TSMC also spent 3 good years to develope a successful 3nm node (N3E).

What Pat Gelsinger and Intel management did not anticipate was a few years of bad PC business since covid-19 and sudden AI investment boom.

In the past few years, one thing I learned is that everything takes a long time in the semiconductor business. Just be patient.
That is the fundamental issue of getting back to process leadership. One or two years ago, I made a comment under his Twitter feed asking why he chose a very risky and expensive strategy and also mentioned Intel should focus on AI. Other analysts argued the fab activities were distractions.

For national security’s sake, there could be other ways to achieve it. They could form a partnership early with TSMC and let them manage their fabs. It could be cost-effective for both companies.

He decided to pursue the most expensive and risky route. Given the consequences, he should take responsibility. At least, he could announce that given the performance, he would cut his compensation by half. As he compared himself to a founder of a company many times, that is what a founder of a company would/should do, in my opinion.
 
I can hardly believe anybody else (other than Pat Gelsinger) could do a better job in terms of returning to foundry leadership in a few short years. Samsung foundry is in deep trouble now, to the point that both TSMC and IFS don't care about them; TSMC also spent 3 good years to develope a successful 3nm node (N3E).

What Pat Gelsinger and Intel management did not anticipate was a few years of bad PC business since covid-19 and sudden AI investment boom.

In the past few years, one thing I learned is that everything takes a long time in the semiconductor business. Just be patient.
I've come to the conclusion that Intel should have followed Larry Ellison's example at Oracle from some years back, and appoint co-CEOs, in Intel's case one for the product groups and one for the fabs. For the design side I think Abhi Talwalkar would be a good candidate. (The current chair of the BoD of Lam Research.) For the manufacturing CEO I would choose Stacy Smith from the Intel BoD.

For BoD chair I would try to get Lip Bu Tan to come back and assume that position. The two business unit CEOs would effectively report to him, and I like all of his opinions about the current version of Intel.

I think these three would make a hell of a leadership team.
 
That is the fundamental issue of getting back to process leadership. One or two years ago, I made a comment under his Twitter feed asking why he chose a very risky and expensive strategy and also mentioned Intel should focus on AI. Other analysts argued the fab activities were distractions.

For national security’s sake, there could be other ways to achieve it. They could form a partnership early with TSMC and let them manage their fabs. It could be cost-effective for both companies.

He decided to pursue the most expensive and risky route. Given the consequences, he should take responsibility. At least, he could announce that given the performance, he would cut his compensation by half. As he compared himself to a founder of a company many times, that is what a founder of a company would/should do, in my opinion.
Fundamentally, there is a difference in seeing where the majority of Intel's value is. Pat G probably thinks it is in the foundry business, and today, a large part (if not the majority) of the investor community seem to think that it is in the products.

I am with Pat G on this matter. TSMC's valuation is $800B+, while AMD is worth $245B today. Note that TSMC is meaningfully discounted because it is a Taiwanese company (in other words, if TSMC were a US company, it would be valued a lot higher), while AMD is probably over valued somewhat.

Now, imagine Intel just close its fab business, and becomes a pure product company. What will happen? Is intel suddenly going to make a lot of money in AI accelerators? No, it will still be a No.3 player at best in AI for quite some time. The market does not place high value with No.3 or even No.2 when the No.1 makes more than 10 times of money than you (just look at Google search v.s bing). X86 business can at best hold its market share when hyperscalers such as AWS and GCP are all developing their own ARM based chips. Also note that, in previous decades, Intel's dominance in CPU business was most likely because it had the best manufacturing technology, and much less because its product design was so much better than competition. Today's Lunar lake success is also most likely due to a superior process node (N3B) v.s. competition.

On the other hand, over the many years in its dominant position, Intel probably has accumulated a lot of R&D potentially crucial in future foundry business (one example is at https://semiengineering.com/the-race-to-glass-substrates/), why just throw them away when returning to technology leadership seems near?
 
I've come to the conclusion that Intel should have followed Larry Ellison's example at Oracle from some years back, and appoint co-CEOs, in Intel's case one for the product groups and one for the fabs. For the design side I think Abhi Talwalkar would be a good candidate. (The current chair of the BoD of Lam Research.) For the manufacturing CEO I would choose Stacy Smith from the Intel BoD.

For BoD chair I would try to get Lip Bu Tan to come back and assume that position. The two business unit CEOs would effectively report to him, and I like all of his opinions about the current version of Intel.

I think these three would make a hell of a leadership team.
I agree with you that in future, Intel probably should split up. I have no opinions who should assume leadership at that time.

Today, Intel products is financially supporting IFS to recover, but IFS is potentially the most valuable business within Intel. This is akin to a family who sacrifice a bit to support their brightest kid to receive the best education. Letting the kid be "on his own" is not the best option as a family.
 
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I agree with you that in future, Intel probably should split up. I have no opinions who should assume leadership at that time.

Today, Intel products is financially supporting IFS to recover, but IFS is potentially the most valuable business within Intel. This is akin to a family who sacrifice a bit to support their brightest kid to receive the best education.
I did not say Intel should split up. I just strongly believe manufacturing and products need two very different kinds of leaders, and I've never been a proponent of PG for either position. Potentially splitting into two companies should wait until IFS is successful and self-funding. That'll probably take several years. I also think manufacturing is Intel's most valuable asset.
 
That is the fundamental issue of getting back to process leadership. One or two years ago, I made a comment under his Twitter feed asking why he chose a very risky and expensive strategy and also mentioned Intel should focus on AI. Other analysts argued the fab activities were distractions.

For national security’s sake, there could be other ways to achieve it. They could form a partnership early with TSMC and let them manage their fabs. It could be cost-effective for both companies.

He decided to pursue the most expensive and risky route. Given the consequences, he should take responsibility. At least, he could announce that given the performance, he would cut his compensation by half. As he compared himself to a founder of a company many times, that is what a founder of a company would/should do, in my opinion.

When it comes to chips for national security and weapon system-related applications, many non-Intel U.S. manufacturers have been providing solutions for a long time. In fact, in several areas, Intel doesn’t have a viable product at all. Intel is trying to make people believe that Intel is the most important, if not the sole, supplier of chips for these critical applications. But this is far from the truth.
 
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