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Just curious how this forum would define a “full node” of scaling these days. Is it Density improvement of X, (and what is X), is it OK if density scaling is less than X but power scaling (efficiency or top end) meets certain criteria? Is there a cost criteria for a full node?
Just curious how this forum would define a “full node” of scaling these days. Is it Density improvement of X, (and what is X), is it OK if density scaling is less than X but power scaling (efficiency or top end) meets certain criteria? Is there a cost criteria for a full node?
Area is no longer the primary factor in defining a full node. Based on TSMC's recent node progression (N7 → N5 → N3E → N2), a full node typically delivers a 10% to 15% increase in performance at the same power level, or reduces power consumption by 25% to 30% while maintaining the same frequency and complexity.
Area is no longer the primary factor in defining a full node. Based on TSMC's recent node progression (N7 → N5 → N3E → N2), a full node typically delivers a 10% to 15% increase in performance at the same power level, or reduces power consumption by 25% to 30% while maintaining the same frequency and complexity.
While you guys are at it, how would you compare Intel 3, 18A, N4P, N3E, and the coming N2 from a PPA point of view, if we ignore these processes' yield differences for now.
Based on public info and various discussions, Intel 4 seems to be roughly at N5P/N4 level; Intel 3 (up to 18% performance at the same power than Intel 4, per Intel) may be better than N4P, but not as good as N3E. Now 18A is said to offer 15% more perf at the same power and 30% more density over Intel 3. N3P is believed to be a minor improvement over N3E.
In late 2023, TSMC said they were assessing N3P is at least as good as 18A from a PPA point of view, does that still hold?
Another confusion I have is that, N3B is said to be more expensive but slightly denser and perhaps a bit more performant than N3E. Does that mean iPhone A18 chip is going to be yet another minor improvement over A17? Last year, A17 was already a disappointment among users.
Area is no longer the primary factor in defining a full node. Based on TSMC's recent node progression (N7 → N5 → N3E → N2), a full node typically delivers a 10% to 15% increase in performance at the same power level, or reduces power consumption by 25% to 30% while maintaining the same frequency and complexity.
TSMC said they are transisitioning to TVO instead of cost per FET as their figure of merit, and based on that 10-15% PPW seems to be what TSMC warrants as a "full node enhancement". At multiple occasions in the past intel has called a 15% PPW enhancement a full node enhancement. Samsung seems to just define it whenever there is a large process change.
If you asked in the 2010s-2020 the answer to that question was around 1.5x or better logic density vs the immediate predecessor (22/20nm planar to finfet being the exception where everyone has collectively accepted 16FF/14LPP/P1270-71 as separate nodes from planar 22/20nm). If you wanted to say what does a full node uplift look like now, seemingly around a 1.4x logic density boost. Claims for SF4 -> SF3 1.27x, i3 -> i18A 1.3x, and N4 -> N3E 1.46x.
Me personally I feel like it is just a gut feeling of how much has changed. intel 10nm to 10nm SF was a whopping 18% PPW increase with like a 800 MHz Fmax increase. Look under the hood and you just find lots of enhancements, by my books this is not a full node even though it is more than a "full node" of performance. SF7 vs SF4E must be a pretty meager demonstrated PPW improvement given how close SF7 matched up to N7 and how poorly even SF4P matches up to N5P. So by the intel and TSMC metrics this is not a full node. However to me that seems stupid since Samsung added major changes such as SDB, COAG, and heavily shrunk MMP and got to similar densities to N5.
TLDR for my money look at the process and just based on the magnitude of the changes it is pretty obvious what is full node innovation and what is a CIP process.
As low as it can go is always best so making that a criteria for how large the cost increase needs to be for it to be a node change doesn't make a ton of sense to me. Granted there are certain heuristics that tend to be true. As the rate of scaling increases the cost increment gets worse. I guess I couldn't say with certainty, but I would bet you that the cost adder from N5 -> N3E is significantly smaller than the cost adder for 16FFC to 10FF. Shot in the dark guess is like 10-20% cost adder for N3E vs 30-40% for 10FF.
