Daniel Payne
Moderator
Web event: Successful GPU IP Implementation on Synopsys HAPS Platforms using ProtoCompiler
Date: February 4, 2015
Time:10:00 AM PST
View attachment 13159
Duration: 60 minutes
GPU IP’s are becoming increasingly large, complex and configurable. There are many variants in each family, single and multi-core, to meet the needs of the wide range of potential end user requirements. Consequently, this requires an equally configurable and flexible FPGA-based prototyping solution to meet the demand for accelerated software development and system validation for the end-application integration. These physical prototyping systems also require a high degree of automation for implementation and partitioning to enable quick prototype bring-up and re-configuration to support other GPU variants for on-going development needs.
Who should attend this webinar:
GPU/ASIC/SoC prototyping and emulation specialists
GPU/ASIC/SoC hardware designers
GPU/ASIC/SoC verification specialists
Speaker:
Andy Jolley
Senior Staff Application Consultant – Worldwide Product Line Lead, FPGA-Based Prototyping at Synopsys
Andy has been working with FPGA technologies for over 25 years, originally in a design capacity in the telecommunications, radar and video industries before supporting FPGA synthesis and prototyping technologies at Synplicity and then Synopsys. Most recently, Andy has been supporting UK customers with their complex CPU SoC and GPU IP prototyping needs on the Synopsys HAPS platforms while also providing support for worldwide engagements to deploy the same SoC and GPU IPs embedded into user applications. Andy holds a 1st Class Bachelor’s Degree in Electronic Engineering from the University of Brighton, England.
Register Online Here
Date: February 4, 2015
Time:10:00 AM PST
View attachment 13159
Duration: 60 minutes
GPU IP’s are becoming increasingly large, complex and configurable. There are many variants in each family, single and multi-core, to meet the needs of the wide range of potential end user requirements. Consequently, this requires an equally configurable and flexible FPGA-based prototyping solution to meet the demand for accelerated software development and system validation for the end-application integration. These physical prototyping systems also require a high degree of automation for implementation and partitioning to enable quick prototype bring-up and re-configuration to support other GPU variants for on-going development needs.
Who should attend this webinar:
GPU/ASIC/SoC prototyping and emulation specialists
GPU/ASIC/SoC hardware designers
GPU/ASIC/SoC verification specialists
Speaker:
Senior Staff Application Consultant – Worldwide Product Line Lead, FPGA-Based Prototyping at Synopsys
Andy has been working with FPGA technologies for over 25 years, originally in a design capacity in the telecommunications, radar and video industries before supporting FPGA synthesis and prototyping technologies at Synplicity and then Synopsys. Most recently, Andy has been supporting UK customers with their complex CPU SoC and GPU IP prototyping needs on the Synopsys HAPS platforms while also providing support for worldwide engagements to deploy the same SoC and GPU IPs embedded into user applications. Andy holds a 1st Class Bachelor’s Degree in Electronic Engineering from the University of Brighton, England.
Register Online Here