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Want to learn 20 nm layout techniques!

J

janetea

New member
A friend was let go from a layout contract job after a week because he could not get up to speed fast enough on 20nm layout. They hired him knowing he did not know how to do it, but due to circumstances, they decided to give him a try. Both of us have been doing Analog Layout design since the early 80's. The past 10+ years we've been in Power Management working on .13, .18, .25 etc.... but nothing like 20nm. I have limited experience with 40nm, but I think 20nm is a different thing altogether.

Is there anyone who explains and teaches what it is, and possibly lessons on layout technique? A workshop, or anything for people who are interested in trying it? Would be nice to add that in a resume to hopefully increase chances of opening things up on the job market for him. And for me, too.

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I’m sorry to hear of your friend’s situation.

Having been in the industry as long as you have you are aware of the trends in the evolution of processes. As the process node shrinks the design rulesand complexity grow exponentially. Your thought regarding lessons or a workshop to learn new processes is a great idea. The Fabs who own those processes will be the roadblock.

The Layout design career needs to evolve and change. Especially this particular field! Layout design isa job that requires continuous learning and yet our educational institutions still have no serious programs for layout design. There are a number of 2 year programs for layout and it truly takes 1-2 years just to become proficient enough to do the standard floorplanning and routing of a typical layout that will be functional after fabrication.

Perhaps we need a certification process similar to what IT professionals use to certify layout designers as experts on specific processes. We would need a foundry to buy-in and provide the means for the certification. This would allow layout designers who may not have had opportunity to work with a process a chance to gain experience and proof to the industry that they can proficiently layout in a particularprocess. We certainly could use certifications in other areas too.

I can say from experience that it is a misconception that having 20+ years’ experience in this field represents proficiency. It is exposure to various processes and even that is not telling. Layout designers need to be smart, fast, and flexible but most of all have a huge capacity and hunger to learn to be the best in this field.
 
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Totaly agree with a certification process for layout designers. Also, it should be open to worldwide not confined within the US.

A brief search in the internet, I only came across with one that offers commercial courses

IC Mask Design - IC Layout and Training Programs

I'm also eager to learn deep submicron layout techniques, any further advices are gladly welcomed.
 
Martin Vaughan • In my humble opinon as a Layout Engineers with more than 10 years experience in both permanent and contract roles it would seem very unfair to give a contract to somebody who clearly explained that he or she had no or limited experience in 20 nM layout techniques was let go after 5 days. I think alot of the engineer community would sympathise with this person in this situation.
Also I should like to point out and in the persons defence that it was the first time he or she would have been involved with FIN transistors as apposed to the planar.

But be warned with Technology node reduction already being implemented from 20nM through to 5nM (2019) during this time frame contractors will be subjected to even more pressure to keep up with the pace of Technology.

Read More white papers.......that's when they get published!!!!!

Martin Vaughan
Layout Consultant for Intel Corporation DE
 
Fergal Brosnan has sent you a message.
Date: 1/08/2013
Subject: 20nm Layout Training
Hello Daniel,

I saw your post on LinkedIn re 20nm layout training. Rather than responding publically, I wanted to drop you a direct line to say that our company, IC Mask Design provides Layout Training, along with Design Services ( IC Mask Design - IC Layout and Training Programs ). Our core expertise is VDSM technology nodes, and we do have a VDSM course that can be targetted to specific technology nodes, with 20nm being one of these. Over 1,300 engineers across 100 organisations have attended our courses to date. The courses are methodology based, so not specifically tied to any EDA environment.

I would be happy to discuss further with you if interested. As mentioned, I wanted to make direct contact with you initially rather than posting a 'plug' of IC Mask Design publically on your discussion.

I look forward to hearing from you.

Fergal Brosnan
CEO, IC Mask Design
 
I would like to share my experience, it may be helpful for your friend.
The foundry has introduced the strain engineering technique to silicon since 90nm technology, the device performance is no longer determined by device itself but also the layout. The layout engineer should understand those Layout Dependent Effect (LDE). It is not limited to WPE and LOD only, there are many other effects should be taken into consideration, such as OSE, PSE ..... The layout engineer should also pay attention to all the dummy insertion, it should enhance the device performance, If the layout engineer just think the layout is simple polygon drawing task, it first results in pre/post-layout mismatch problem, it takes many layout iterations to achieve the desired performance target, the actual silicon performance is greatly degraded. Intel has published few papers to describe the layout techniques for 40nm technology. For 20nm process, the foundry implements the double pattern (DP) to resolve the litho problems, it makes the layout even harder. DP is based on color graph theory, the layout engineer should aware of the wire spacing and avoid the close loop formation, otherwise, it results in huge amount of DRC errors. Finally, the traditional analog layout technique doesn't fully work for 28nm below. For example, the centroid layout is recommended for device matching, however, the high metal resistance greatly degrades the circuit performance, the layout engineering should aware the technology changes.
 
Oscar, thank you so much. I really enjoy learning about it. Hopefully someone comes along that knows how to go about learning it hands on, too. Having said that, it is helpful to explain an understanding to an employer to show some initiative and interest.
 
Hi Ginger, I know you are speaking in general terms, but I am confident that I fall in to the category of wanting to evolve and change! This is a motivator for me. You describe perfectly in my opinion, the qualities a modern layout designer should have. I have seen the opposite and it does eventually force them in to retiring.
 
Hi Martin,

My friend's former boss spoke to the 20nm layout group's hiring manager, so that's why he was given a chance. I dont know what the former boss said to hiring manager, but I guess as a favor they wanted to give him a chance. It seems strange to me, too, but I dont know the minor details of who said what and then why he was let go.
 
Oh, and Martin.... I believe he sitting there on his own trying to learn it. At the end of 5 days, the manager changed his mind. They dont want to have to train anyone. But there aren't a lot of layout designers right now with this experience.
Seems like would have helped to have read more about it, done some research first and maybe self teaching would be enhanced with this prior knowledge and some frame of referance
 
Janetea - in my experience (I work now for an EDA tool vendor, and my main background in device physics), in power management, and in analog design in general, there are so many layout things that are left out from the analysis and optimization, due to the layout complexities. Even in "older" technologies, there are many physical effect, affected by the layout, and that affect IC performance and reliability - current crowding (sharp concave corners, metal slotting, ...), distributed effects, unbalanced current in solder bumps and copper pillars, interaction between device/chip/package/PCB, distributed gate delay effects, etc. etc. When I am showing pictures of the current flow and potentials on top of the layout, that is often an "aha" moment - even for people who are doing layout designs for decades. In more advanced nodes, this is going to bite hard - metal and contacts/via resistances are shooting up (example - in 28 nm process, contact resistance is about 100-200 Ohm!), there are more DR constraints (example - aggressive metal slotting), and so on.Unfortunately, there are no good deep books on layout best practices (the best of them - Alan Hastings' book, does not cover power management in detail), there are no such courses, very few tutorials, and a learning form real experience takes a lot of time...
 
Hi Maxim,

you wrote: >>there are no such courses, very few tutorials, and a learning form real experience takes a lot of time...<<<

Those 2 comments are at the top of my awareness, as to the way I understand things to be. One needs real experience and it takes a lot of time. Thus, my reason for wanting to blast this out in to the message board hemisphere.
I absolutely enjoy hearing everyone's input. I heard from someone today who says their company teaches advanced Analog and sub-micron layout. So we'll see on that. You packed a lot of good information in your post that I should know and look in to further. Thank you very much!
 
Sorry to hear about your friends difficulty. It is truly unfortunate for all involved, that it went the way it did. As you've no doubt gathered from the replies, our Layout world is ever evolving and requires constant learning to remain an active contributor. Not just in products, tools and technologies, but as your friend learned, in layout techniques. Unfortunately, outside of a specific manufacturer or design house, there are no courses to my knowledge offering 'layout technique' training for state of the art technologies. Therefore every Layout Designer must posses observing and learning skills to be pick up and apply these special techniques to new technologies or product lines. Building upon the trust of your employer (be it as a direct employee, contractor or consultant) will ensure that exposure to and 'training' in the latest technologies is currently the best avenue to staying on top of the industry needs.

I wish there were more courses available to help educate a broader Layout audience .. on the fine art of DFM, DFM, DFT and just general design for a successful and functional product design.
 
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Martin Vaughan • Yes I think in principle it would be a good idea to be certified as long as its readily available worldwide and the training costs are not too high.
Usually either a foundry, EDA tool provider or IC Mask will charge, that’s ok if your employee with a company but if your self employed then you would need to pay and training is never cheap.
Maybe in some cases if a contractor is already placed with a client and companies next project is in 20nM maybe the company should understand the need for training and assist the contractor.

As for the layout engineer let go after only 5 days I think the PDK spec for 28nM is around 480 odd pages long I think you would need a little more than 5 days just to understand what was required. With reference to 20 nM cant comment as I haven’t seen the PDK!
Also Im a little concerned that IC Mask can offer training courses in 20nM as I dont no anybody with my division has attempted an anlogue layout in 20nM.....yet!

In response to Jane tea I believe the only layout engineers with 20nM experience will be TSMC, Global Foundries and Intel feel free to correct me if I’m wrong!
 
Nikhil Shah • Sooner or later most of the companies who use fabless model will need to ramp up to 28nm or below technologies then they will have to train the contractors or face a situation where the market wants their product fast but they can not find good engineers to work on the layout hence missing on the revenue opportunities.
 
The top fabless companies are laying out 20nm right now. Qualcomm, Nvidia, Broadcom, Altera, Xilinx, Marvell, etc... 20nm is taping out this quarter as a matter of fact. Certainly TSMC and the other foundries were first with SRAM and foundation IP.
 
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Martin Vaughan • In my humble opinon as a Layout Engineers with more than 10 years experience in both permanent and contract roles it would seem very unfair to give a contract to somebody who clearly explained that he or she had no or limited experience in 20 nM layout techniques was let go after 5 days. I think alot of the engineer community would sympathise with this person in this situation.
Also I should like to point out and in the persons defence that it was the first time he or she would have been involved with FIN transistors as apposed to the planar.

But be warned with Technology node reduction already being implemented from 20nM through to 5nM (2019) during this time frame contractors will be subjected to even more pressure to keep up with the pace of Technology.

Read More white papers.......that's when they get published!!!!!

Martin Vaughan
Layout Consultant for Intel Corporation DE
 
Justin Fisher • I concur with Martin. Good luck finding a contract engineer who can walk in and start laying out FinFET technology on day 1. The TSMC 28nm planar process design manual is the largest design manual I've ever seen.

Irrespective of hiring a permanent guy or a contractor, the hiring company/manager needs to realize that time is going to be required for that person to come up to speed. 5 days isn't enough. This speaks to be more of management incompetence than engineering incompetence.

I'd love to know who the company was - though I'm fairly sure I can guess...
 
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