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TSMC grows partnership with Ansys to provide advanced power integrity and electromigration signoff tools for next-generation applications Key Highlights Ansys® RedHawk-SC™ is certified for TSMC's advanced 3nm process technology Ansys' comprehensive power, thermal, and reliability analysis...
Certified Synopsys design solutions enable HPC, mobile, 5G, and AI SoCs and offer cutting-edge power savings and performance MOUNTAIN VIEW, Calif., Aug. 25, 2020 /PRNewswire/ -- Highlights: Requirements in growth semiconductor segments are driving the state-of-the-art in silicon process...
Synopsys 3DIC Compiler platform reduces design turnaround time for chip-package co-design implementation MOUNTAIN VIEW, Calif., Aug. 25, 2020 /PRNewswire/ -- Highlights: TSMC certifies CoWoS® and InFO design flows based on the Synopsys 3DIC Compiler unified platform 3DIC Compiler...
SANTA CLARA, Calif. – August 25, 2020 – Marvell (NASDAQ: MRVL), a leading provider of data infrastructure semiconductor solutions, today announced an extension of their long term partnership with TSMC (TWSE: 2330; NYSE:TSMC), the world’s largest dedicated semiconductor foundry, to deliver a...
NRZ-based die-to-die connectivity IP addressing cost-effective, multi-chip applications supports organic substrate packaging SAN JOSE, Calif., 24 Aug 2020 Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the availability of its silicon-proven Cadence® UltraLink™ D2D PHY IP on the...
Companies broaden collaboration to continue advancing mobile, AI and hyperscale electronics innovation SAN JOSE, Calif., 25 Aug 2020 Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that its digital full flow and custom tool suite has been optimized for TSMC’s 3nm (N3) process...
Customers creating multi-chip(let) advanced packages for hyperscale and networking applications can achieve accelerated productivity through streamlined design, analysis and verification reference flows SAN Jose, Calif., 25 Aug 2020 Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced...
Posted on August 24, 2020 Rani Borkar Corporate Vice President, Azure Hardware Systems and Infrastructure Right now, every industry and every customer is going through a massive transformation, and cloud computing is often a central enabler of this. The silicon industry is also experiencing...
Key Highlights Ansys achieved certification of its advanced semiconductor design solution for TSMC's high-speed CoWoS® (Chip-on-Wafer-on-Substrate) and InFO (Integrated Fan-Out) 2.5D and 3D advanced packaging technologies Ansys' comprehensive suite of power, thermal and signal integrity...
TSMC Application Specific Platforms:
- Smartphone: Speed, power, and area
- Automotive: Reliability, functional safety, Standard compliance
- HPC: Sustainable performance, memory bandwidth, Reliability
- IoT: Ultra low power and ultra connectivity
Process Density Scaling:
N7 to N6 1.18x
N7 to N5 1.83x
N5 to N3 1.7x
Process Performance Scaling:
N7 to N6 +2%
N7 to N5 +13%
N5 to N3 +11%
Process Power Scaling
N7 to N6 -10%
N7 to N5 -21%
N5 to N3 -27%
N5 IP portfolio is fully ready for tape-outs
N3 is EDA tool/IP certified and ready for design
Automotive Development Platform
16nm -> N7-> N5 (2022)
Technology, design flow, manufacturing, and IP ecosystem
Qualification:
-tighten intrinsic reliability criteria
- target for grade-1 with stress at 125C
Design collaterals:
-SPICE Model - S2S accuracy
-aging model - reliability
- Auto DRM / EM Low DDPM
Design flow for automotive:
Additional reliability checks on device/metal degradation for automotive mixed signal design
Full automotive design enablement platform
IoT Platform
TSMC offers comprehensive low power platforms for IoT for a wide range of IoT applications
.18m eLL, 90nm ULP, 55ULP, 45 ULP, 22ULP, 22LL, and the new N12e FinFET
N12e is EDA and IP ready for Ultra Low Power Designs
TSMC 3D Fabric
Design ecosystem is ready to support chip, package, and systems implementation and verification.
- InFO Package Design Solution
- CoWos Package Design Solution
- TSMC-SoIC Design Solution
- Package-Chip Integration and Verification
- 3D Fabric Design Solution Readiness
Summary
- N3 continues PPA trend for both smartphone and HPC applications. Design solution is ready for PPA exploration
- N5, N6, and N7 design solutions and ecosystem are ready and used for production chips
- Developed comprehensive automotive design ecosystem on N16 and N7. Will extend to N5 in 2022
- N12e enables further speed and enhancement to support AI enabled IoT products
- Built comprehensive 3D Fabric design platform to enable more system performance
New technologies driven by AI and Data-centric Industry Trends
Lip-Bu Tan, Cadence CEO and Investor Extraordinaire
Five generation trends:
5G
Hyperscale
Industrial IoT
AI
Data is Driving a Silicon Renaissance
- data analysis
- data transmission
- data processing
- data storage
TSMC, Arm, Cadence collaboration
- EDA flow certification for N3
- IP and EDA flow certification for TSMC N6 and N5
- Optimized EDA flow for Arm Cortex N7 and N5
- DDR5/LPDDR5 IP for N5 hyperscale and automotive
- 112/56 SerDes for N6 and N5 datacenter chips
- 3D IC collaboration on 2.5 and 3D IC flows
- Clarity Solver certified for CoWos flow
Benefits
- Advanced technologies
- Silicon proven IP
- Optimized design flows
- Cloud enabled (Cadence and TSMC have a serious cloud partnership)
Synopsys Fusion
P&R, Synthesis, timing, power, test, physical verification, etc...
- 2x+ faster from RTL to GDSII
- Better performance
- Lower power
- Smaller area Applied to TSMC advanced technologies
Fusion understands manufacturing and Test
Fusion can then go up to architecture
Louis Sullivan (architect considered father of sky scrapers) "Form follows function"
A principle associated with late 19th and early 20th century architecture and industrial design in general, and it means the shape of a building or object should primarily relate to its intended function or purpose.
Frank Lloyd Wright (fellow architect) "Form and function should be one"
Reinventing the World - One Process Node at a Time
Joseph Sawicki, Executive VP, Mentor
Historical SoC example:
2013 28nm, die size 102mm2, 1 billion transistors, speed 269 (Geekbench single core)
2019 7nm, die size 98mm2, 8.5 billion transistors speed 1331 (geekbench single core)
Graphcore AI accelerator for the cloud @ 23 billion transistors, a serious test and verification challenge if not for OIP
"Moore's Law is not Dead, or even sick, TSMC thinks it can hold up Moore's Law for decades"
TSMC and Mentor Addressing OIP Ecosystem Reliability
- Latchup (LUP) Methodology
- ESD Verification
- Calibre PERC
Silicon Creations Example:
Delivered >300 IP with TSMC down to N3
200+ different PLL designs
500+ customer chips in production at TSMC
IP Targets:
Automotive
Aerospace
Consumer
Data Center
Industrial
IoT
Tanner: Silicon Photonics and Partnership with TSMC
- MEMS, AMS, Silicon Photonics
MEMS/IC Co-design
Draw and edit
Curved geometries
- AMS
Full custom AMS design flow
Integrated with other Mentor tools
- Silicon Photonics
Complete photonics with electronics design
Integrates with leading photonics simulation tools
More than Moore Silicon
- Calibre 3D Stack verification environment
- Integration with between Calibre and Xpedition packaging
