You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
While Intel has been busy making bets on its 18A node as part of its accelerated roadmap towards chip making dominance, TSMC appears to have been beavering away in the background to undercut it.
Adding the Super Power Rail in the A16 is a smart move for TSMC. It aligns with TSMC's strategy of not introducing two major technical breakthroughs in a single node. Additionally, the timing is favorable since the A16's release coincides with the ramp-up to Intel 18A's HVM, making 18A less attractive.
While Intel has been busy making bets on its 18A node as part of its accelerated roadmap towards chip making dominance, TSMC appears to have been beavering away in the background to undercut it.
This article is poorly written. It says TSMC will start using "Super Power Rail" in A16 process in 2026 thus undercutting Intel's PowerVia which will be available in 2027. The source for 2027 reference is an article from PcGamer which talks about Intel 10A (1nm) process. It appers that the author has no clue and believes that the first Intel process with PowerVia is going to be 10A.