Did I read this right? Did Future Horizon’s CTO just question Dr. Morrris Chang’s integrity? And EETimes prints it? How else would you interpret this article published by last Friday (1/20/2012)?
TSMC's 28-nm process in trouble, says analyst
LONDON – Mike Bryant, technology analyst with Future Horizons Ltd. has said that foundry Taiwan Semiconductor Manufacturing Co. Ltd. is in trouble with its 28-nm manufacturing process technologies, which are not yet yielding well. Bryant referenced un-named contacts made with multiple companies waiting for designs to be produced by TSMC on 28-nm processes. Bryant said that there are 10 designs in manufacture from seven companies. "We're now hearing none of them work; no yield anyway,"
Ah, the old un-named contacts ploy, tabloid journalism 101. This is déjà vu 40nm ramping. The 40nm yield ramp was longer than 65nm so it must be TSMC’s fault, right? Of course the only people questioning 28nm yield are so called industry analysts and editors, not the people who actually do 28nm design and manufacturing.
Let me tell you this from my personal experience, there is working TSMC 28nm silicon all over Silicon Valley if you care to look. 28nm FPGAs are already shipping to customers. Other working 28nm silicon includes a microprocessor, GPUs, and several wireless SoCs from industry leading providers. The word on the street in Silicon Valley, from the people who actually taped out in 28nm, tracks with what Morris Chang said in the Q4 conference call which you can read HERE.
I will say a few words on the status of our 28-nanometer ramp. Our 28-nanometer entered volume production last year and contributed 2% of 4Q '11s wafer revenue. Defect density and new progress is ahead of schedule and is better than 40-45-nanometer at the corresponding stage of the ramp-up. We expect 28-nanometer ramp this year to be fast and we expect 28-nanometer will contribute more than 10% of total wafer revenue this year. Our tape-outs on the 28-nanometer, we have so far completed 36 individual tape-outs and have scheduled another 132 individual product tape-out in 2012. While three versions of the 28-nanometer technology, the LP, the HP and the HPL have entered volume production, the fourth version, the HPM, has entered risk production this quarter and is expected to begin volume production in the second half of this year……… Dr. Morris Chang
Anybody else bothered by this? Is there really a place for tabloid journalism amongst semiconductor professionals? I would unsubscribe to EETimes for printing it but I already did that after the 3D IC debacle.
D.A.N. (Blogger, not a Journalist)
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TSMC's 28-nm process in trouble, says analyst
LONDON – Mike Bryant, technology analyst with Future Horizons Ltd. has said that foundry Taiwan Semiconductor Manufacturing Co. Ltd. is in trouble with its 28-nm manufacturing process technologies, which are not yet yielding well. Bryant referenced un-named contacts made with multiple companies waiting for designs to be produced by TSMC on 28-nm processes. Bryant said that there are 10 designs in manufacture from seven companies. "We're now hearing none of them work; no yield anyway,"
Ah, the old un-named contacts ploy, tabloid journalism 101. This is déjà vu 40nm ramping. The 40nm yield ramp was longer than 65nm so it must be TSMC’s fault, right? Of course the only people questioning 28nm yield are so called industry analysts and editors, not the people who actually do 28nm design and manufacturing.
Let me tell you this from my personal experience, there is working TSMC 28nm silicon all over Silicon Valley if you care to look. 28nm FPGAs are already shipping to customers. Other working 28nm silicon includes a microprocessor, GPUs, and several wireless SoCs from industry leading providers. The word on the street in Silicon Valley, from the people who actually taped out in 28nm, tracks with what Morris Chang said in the Q4 conference call which you can read HERE.
I will say a few words on the status of our 28-nanometer ramp. Our 28-nanometer entered volume production last year and contributed 2% of 4Q '11s wafer revenue. Defect density and new progress is ahead of schedule and is better than 40-45-nanometer at the corresponding stage of the ramp-up. We expect 28-nanometer ramp this year to be fast and we expect 28-nanometer will contribute more than 10% of total wafer revenue this year. Our tape-outs on the 28-nanometer, we have so far completed 36 individual tape-outs and have scheduled another 132 individual product tape-out in 2012. While three versions of the 28-nanometer technology, the LP, the HP and the HPL have entered volume production, the fourth version, the HPM, has entered risk production this quarter and is expected to begin volume production in the second half of this year……… Dr. Morris Chang
Anybody else bothered by this? Is there really a place for tabloid journalism amongst semiconductor professionals? I would unsubscribe to EETimes for printing it but I already did that after the 3D IC debacle.
D.A.N. (Blogger, not a Journalist)
<script src="http://platform.linkedin.com/in.js" type="text/javascript"></script>
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