Kevin Gibb
Product Line Manager, Process
TechInsights has been on the hunt for some time now for Samsung’s 20 nm DDR4 DRAM, and we have finally found them populated on a 32 GB registered dual in-line memory module (RDIMM). The module is populated on both sides with 36 K4A8G045WB 8 Gb DDR4 DRAM chips.
View attachment 13752
Figure 1: Samsung 32 GB 20 nm DDR4 Memory Module
Each of the DRAM packages contains a single 5.8 mm x 9.7 mm large die as seen in Figure 2. Our curiosity is peaked by the small pads seen adjacent each bond pad. These are just visible in Figure 2, but are readily seen in the enlarged image, Figure 3.
View attachment 13751
Figure 2: Samsung 20 nm DDR4 Die Photograph
Samsung’s product literature for its 32 GB RDIMM makes reference to future capacity expansion to 128 GB using 3D through silicon vias (TSV) to stack the 8 Gb dies one on top of the other. The dies will likely be bumped together with a bump structure to these small TSV bond pads shown in Figure 3, and through silicon vias will be used to enable die stacking.
View attachment 13753
Figure 3: TSV Bond Pads
Figure 4 is a SEM cross section through one of the TSV bond pads. The pad is about 30 µm in diameter and a 14 µm central area is free of polysilicide structures on the surface of the silicon substrate. The area outside this central region is patterned with STI and polycide and these may be used to relieve stresses that accompany the TSVs. The TSVs themselves, when implemented, will almost certainly to be less than 14 µm in diameter, possibly as small as 8 µm. The mismatch in thermal expansion coefficients between the TSV fill material (Cu or W) and the silicon die and dielectric layers has been a cause for reliability concerns for some time. Samsung has placed a large number of tall W vias just outside the right edge of the TSV pad area. There are considerably more of them just outside the view of Figure 4 suggesting that they are being used to add mechanical strength to the dielectric stack.
View attachment 13754
Figure 4: TSV Landing Pads in Cross Section
Figure 5 is an enlarged view of the left side of the TSV region. A copper metal 2 plate will likely be the land for the TSV that will be laser drilled from the backside of the die in a via last process. This copper pad is connected by tungsten filled vias to the overlying aluminum TSV bond pad. A patterned metal 3 lies between metal 2 and metal 4 that are likely being used for stress relief.
View attachment 13755
Figure 5: Edge of TSV Region
This DDR4 is now in our labs for analysis and we will be publishing a structural analysis report on the device in the near future. In the meantime, we are on the hunt for the 128 GB RDIMM with the stacked dies.
Having trouble viewing images? View them here.
TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM
Product Line Manager, Process
TechInsights has been on the hunt for some time now for Samsung’s 20 nm DDR4 DRAM, and we have finally found them populated on a 32 GB registered dual in-line memory module (RDIMM). The module is populated on both sides with 36 K4A8G045WB 8 Gb DDR4 DRAM chips.
View attachment 13752
Figure 1: Samsung 32 GB 20 nm DDR4 Memory Module
Each of the DRAM packages contains a single 5.8 mm x 9.7 mm large die as seen in Figure 2. Our curiosity is peaked by the small pads seen adjacent each bond pad. These are just visible in Figure 2, but are readily seen in the enlarged image, Figure 3.
View attachment 13751
Figure 2: Samsung 20 nm DDR4 Die Photograph
Samsung’s product literature for its 32 GB RDIMM makes reference to future capacity expansion to 128 GB using 3D through silicon vias (TSV) to stack the 8 Gb dies one on top of the other. The dies will likely be bumped together with a bump structure to these small TSV bond pads shown in Figure 3, and through silicon vias will be used to enable die stacking.
View attachment 13753
Figure 3: TSV Bond Pads
Figure 4 is a SEM cross section through one of the TSV bond pads. The pad is about 30 µm in diameter and a 14 µm central area is free of polysilicide structures on the surface of the silicon substrate. The area outside this central region is patterned with STI and polycide and these may be used to relieve stresses that accompany the TSVs. The TSVs themselves, when implemented, will almost certainly to be less than 14 µm in diameter, possibly as small as 8 µm. The mismatch in thermal expansion coefficients between the TSV fill material (Cu or W) and the silicon die and dielectric layers has been a cause for reliability concerns for some time. Samsung has placed a large number of tall W vias just outside the right edge of the TSV pad area. There are considerably more of them just outside the view of Figure 4 suggesting that they are being used to add mechanical strength to the dielectric stack.
View attachment 13754
Figure 4: TSV Landing Pads in Cross Section
Figure 5 is an enlarged view of the left side of the TSV region. A copper metal 2 plate will likely be the land for the TSV that will be laser drilled from the backside of the die in a via last process. This copper pad is connected by tungsten filled vias to the overlying aluminum TSV bond pad. A patterned metal 3 lies between metal 2 and metal 4 that are likely being used for stress relief.
View attachment 13755
Figure 5: Edge of TSV Region
This DDR4 is now in our labs for analysis and we will be publishing a structural analysis report on the device in the near future. In the meantime, we are on the hunt for the 128 GB RDIMM with the stacked dies.
Having trouble viewing images? View them here.
TechInsights - Samsung 20 nm DDR4 TSV Enabled DRAM
