Tackling large-scale SoC and FPGA prototyping debug challenges

[Daniel Payne]

I've met and interviewed Brad Quinton at Tektronix here in Beaverton, Oregon and he just wrote an article at EE Times: Tackling large-scale SoC and FPGA prototyping debug challenges. Brad summarizes the core requirements for optimal SoC debugging:

• Full RTL-level visibility with minimal dependence on FPGA CAD flows
• Fast, efficient identification of the root cause of bugs
• Run at full speed to enable verification with real-world signals
• Time-correlated signals across different clock domains
• Scale seamlessly to support large, complex designs
• Enable efficient debugging of firmware and application-level software
• Verify hardware and software interactions at the system-level

Three approaches have traditionally been applied to SoC debug:

• Simulation acceleration
• Emulation
• FPGA-based prototyping

There are big issues with each of these approaches, however Brad's group has come up with something new for the third approach, FPGA-based prototyping by adding instrumentation efficient enough to allow hundreds of thousands of probes to be used, instead of a thousand probes (ie. ChipScope and SignalTAP).

Read the full EE Times article, or some of the Wiki pages here:

• Engineer to Engineer, Embedded Instrumentation
• Apply within: four embedded instrumentation approaches
• ASIC Prototyping: Dini Group and Tektronix
• Embedding 100K probes in FPGA-based prototypes
• Improving FPGA Prototype Debugging

Have you tried FPGA-based prototyping, and if so how was the debug process for you? Fun or painful?

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[ali.akhtar]

Debug process was mostly painfull. You simply don't have enough resources in an FPGA to log the whole set of signals. When you have limited visibility and Intermittent failures, the process becomes increasingly painfull. I have only used Xilinx tools so Not sure if Sysnopsys FPGA toolset has similar limitations.

 

[Daniel Payne]

Ali,

Thanks for sharing your debug process using a Xilinix FPGA and tools.

 

[Xiin]

I am using Synopsys Haps-6x FPGA prototyping boards. Our design was partitioned into 4 Vertex6 by using Synopsys Certify. Many cables among them. And also, I am using Synposys Identify to bring some signals out to watch for debugging. Will move to Vertex7 soon. They have Haps-7 coming out.

Debug process was mostly painfull. You simply don't have enough resources in an FPGA to log the whole set of signals. When you have limited visibility and Intermittent failures, the process becomes increasingly painfull. I have only used Xilinx tools so Not sure if Sysnopsys FPGA toolset has similar limitations.

 

[Daniel Payne]

Xiin,

How is the debug going with your HAPS system?

 

[Xiin]

Pretty good. The main difficulty is that the timing crossing the FPGAs through the cables.

Xiin,

How is the debug going with your HAPS system?

 

[Daniel Payne]

So does the effect of the cables mean that your system speed is slowed down, or what?

 

[Xiin]

Yes, slower much much down.
But the goal is to verify the function. Slowing down is acceptable.

So does the effect of the cables mean that your system speed is slowed down, or what?