System Verilog : Ignoring function's return value!

[Asic With Ankit]

Dear Readers,

functions and tasks are the very useful features in Verilog/System Verilog. We have been using these features since long in our test bench development.

Though 'function' is available in verilog as well as in System Verilog, there is difference! Now you may want to know what is that difference.

Let me first explain you the differences between task and functions for Verilog language :

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1. Tasks can consume time while a function can not which means..

• tasks can have delays #50 while functions can not have.
• tasks can also have blocking statements such as @(posedge clock) or wait (xyz) while functions can not have.
• tasks can call functions while reverse case is not allowed (function can not call task)

Now let us understand what is the difference between usage of function in verilog and system verilog?

Verilog must return a value and a value must be used but In System Verilog If you want to call a function and ignore its return value, you can cast the result to void.

Conclusion :

If you have System Verilog task that does not uses or consume time, we should make it a void function. If you do this, you are free to use this this functions from any task or functions. This is the reason people are using debugging routine as void function rather than a task so that it can be called from any task or function:

For Example:

function void print_value (...........);
$display ("Value of A=%h B=%h C=%h", $time);
endfunction

Here we can see the syntax of usage, $display is not a time consuming feature and at the same time we don't have any other time consuming statements as discussed earlier like delays, blocking statement... This type of function does not need return value to be used. This will ignores returns value.

Hope this is a useful post to understand basic difference between functions and tasks in System Verilog.

Keep Reading & Sharing,
ASIC With Ankit

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[simguru]

Another way to look at tasks vs functions is that tasks have a persistent context, functions do not. Calling a task is like starting a new thread in the context of its module instance and waiting for it to complete, a function call creates a temporary context (which may be just a stack frame) that will be destroyed on its completion. Verilog gets some of its speed from the fact it doesn't have to manage function call stacks independently of the normal machine calling mechanisms.

VHDL allows functions to suspend (or "consume time") which can make for inefficient code generation if you don't know whether you sub-calls will suspend or not. To optimize around that you need to do call-tree analysis at run-time (post elaboration), and have the two flavours of compiled code available.

From a language design perspective it's probably easier to make everything functions (as in VHDL), but to prefix calls with a keyword like "task" to indicate you are expecting that it might require to suspend. That way the code is polymorphic, the compiler can generate suspending and non-suspending versions and usage is up to the user - with errors being thrown if a a function attempts to suspend in a non-task stack.

 

[pfw3001]

hi Ankit

Actually, function could call task which do not include timing in Systemverilog.