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Summary of MOS-AK Compact Modeling Workshop from March 2014

Daniel Payne

Moderator
MOS-AK Compact Modeling WorkshopLondon Metropolitan UniversityMarch 28-29, 2014 London

The MOS-AK/GSA Modeling Working Group, a global compact modeling standardization forum, delivered its annual spring compact modeling workshop on March 28-29, 2014 at London Metropolitan University. The event received full sponsorship from leading industrial partners including Agilent Technologies, MOSIS Services and Tanner EDA. The technical MOS-AK program promoters included Eurotraining, IET, IEEE UKRI Section as well as EDA Solutions. More than 40 registered academic researchers and modeling engineers attended two sessions to hear 9 technical compact modeling presentations including the QUCS Tutorial by Prof. Mike Brinson.


The MOS-AK/GSA speakers have discussed following compact modeling and Verilog-A standardization topics:

  • Wavelength dependent microwave devices based on metamaterial technology (Bal Virdee; London Metropolitan University; UK)
  • Development of Verilog-A models for silicon photonics devices and implementation in a standard EDA environment (Patrick Martin; CEA, Leti; F)
  • A New MOSFET Model for the Simulation of Circuits under Mechanical Stress (Thomas Gneiting; AdMOS GmbH; D)
  • Modeling the channel charge and potential in quasi-ballistic nanoscale DG MOSFETs (Anurag Mangla; EPFL; CH)
  • The EPFL Junctionless FETs model (Farzan Jazaeri; EPFL; CH)
  • On the modelisation of the main characteristics of SOI Hall cells by three-dimensional physical simulations (Maria-Alexandra Paun, University of Cambridge ; UK)
  • Compact modelling of RF small-signal and noise performance with EKV3 MOS transistor model (Matthias Bucher, TUC; GR)
  • Modeling of GaN-based High Electron Mobility Transistors - A Cursory Note on Some Latest Developments (Brian Chen, Agilent; US)
  • Building a second generation Qucs GPL circuit simulator: package structure, simulation features and compact device modelling capabilities (Mike Brinson, London Metropolitan University; UK)

The presentations are available for downloads here.


The MOS-AK tutor, Prof. Mike Brinson, has delivered invited Qucs tutorial "Building a second generation Qucs GPL circuit simulator: package structure, simulation features and compact device modelling capabilities" drawing a roadmap of future of the open source, GPL CAD/EDA tools development directions. Introducing the opne source, GPL simulator developments, Prof. Brinson has referred to recent Larry Nagel's MOS-AK keynote talk "SPICE in the Twenty-First Century" and recalled main directions of the next generation GPL circuit simulators. Several available open source simulators have already contain one or more of these improvements, as listed below, but in many cases they have not yet been migrated to generally available open source versions:



  • Open source tools
  • Run on popular hardware, including PCs, Laptops as well as Tablets
  • Employ Verilog-A for emerging technology model development
  • Include RF circuit simulation
  • Include statistical circuit analysis
  • Include thermal circuit analysis
  • Include system simulation

These new development directions are important to take Qucs simulator as well as other open GPL CAD/EDA tools to an improved level of performance with expanded simulation and modelling facilities. Planing further improvements it is critical to have in mind last four decades of the circuit simulators developments. The Table.1 presents two parallel branches of the simulation tools developments with a clear trend towards open source, GPL developments targeting high/radio frequency (RF) IC design support and circuit applications.




TAB.1: Circuit Simulator Development Time Line
[table]
|-
| valign="top" | SPICE BRANCH

| valign="top" | YEAR

| valign="top" | RF BRANCH

|-
| valign="top" | SPICE1

| valign="top" | 1973

| valign="top" |


|-
| valign="top" | SPICE2

| valign="top" | 1975

| valign="top" |


|-
| valign="top" | HSPICE

| valign="top" | 1981

| valign="top" |


|-
| valign="top" | PSPICE

| valign="top" | 1984

| valign="top" |


|-
| valign="top" | ELDO

| valign="top" | 1984

| valign="top" |


|-
| valign="top" |


| valign="top" | 1988

| valign="top" | MDS

|-
| valign="top" | SPECTRE

| valign="top" | 1989

| valign="top" |


|-
| valign="top" | SPICE3 (GPL)

| valign="top" | 1989

| valign="top" |


|-
| valign="top" |


| valign="top" | 1991

| valign="top" | LIBRE

|-
| valign="top" |


| valign="top" | 1994

| valign="top" | ADS

|-
| valign="top" |


| valign="top" | 1996

| valign="top" | SPECTRE RF

|-
| valign="top" |


| valign="top" | 1998

| valign="top" | ELDO RF

|-
| valign="top" | SPICEOPUS

| valign="top" | 1999

| valign="top" |


|-
| valign="top" |


| valign="top" | 2003

| valign="top" | QUCS (GPL)

|-
| valign="top" |


| valign="top" | 2004

| valign="top" | HSPICE RF

|-
| valign="top" | NGSPICE (GPL)

| valign="top" | 2008

| valign="top" |


|-
| valign="top" |


| valign="top" | 2012

| valign="top" | QUCSSTUDIO

|-
| valign="top" | Xyce (GPL)

| valign="top" | 2013

| valign="top" |


|-
| valign="top" |


| valign="top" | 2014

| valign="top" |


|-
[/table]


Recent, Qucs and other simulators, enhanced ADMS/Verilog-A modeling support is a new trend to watch. The AMDS is only open source compact model synthesizer available, now. The ADMS, a new open-source tool that enables fully automatic synthesis of compact models into a target circuit simulator. ADMS takes Verilog-A compact model descriptions as input and generates C code that matches model/simulator interfaces of the target simulator. Table.2 shows current status of the ADMS tool adoption among selected open source, GPL simulators, including QUCS, ngspice, Xyce and SpiceOPUS.


TAB.2: Open Source CAD/EDA tools for the device and circuit macromodeling
[table]
|-
| rowspan="2" valign="middle" | Simulator

| colspan="2" valign="top" | Qucs-0.0.18

| colspan="2" valign="top" | ngspice-26

| colspan="2" valign="top" | Xyce-6.0

| colspan="2" valign="top" | SPICEOPUS-2.31

|-
| valign="top" | EDD

| valign="top" | Verilog-A[SUP]1[/SUP]

| valign="top" | B

| valign="top" | Verilog-A[SUP]2 [/SUP]

| valign="top" | B

| valign="top" | Verilog-A[SUP]3 [/SUP]

| valign="top" | B



| valign="top" | Verilog-A[SUP]4[/SUP]



|-
| valign="top" | Operators
Arithmetic functions

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


|-
| valign="top" | ABS

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


|-
| valign="top" | DDT

| valign="top" | X

| valign="top" | X

| valign="top" |


| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


| valign="top" |


|-
| valign="top" | DDX

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


| valign="top" |


|-
| valign="top" | IF

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


| valign="top" |


|-
| valign="top" | POW

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


|-
| valign="top" | RND

| valign="top" | X

| valign="top" |


| valign="top" | X

| valign="top" |


| valign="top" | X

| valign="top" | ?

| valign="top" |


| valign="top" |


|-
| valign="top" | SQRT

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


| valign="top" | X

| valign="top" |


|-
| valign="top" | TABLE

| valign="top" |


| valign="top" |


| valign="top" | X

| valign="top" |


| valign="top" | X

| valign="top" |


| valign="top" |


| valign="top" |


|-
| valign="top" | Exponential, logarithmic
and trigonometric functions

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" | X

| valign="top" |


|-
[/table]


Implementation notes:

  • DC, AC, AC noise, S parameters, TRAN and HB
  • DC, AC and TRAN
  • DC, AC, TRAN and HB
  • Not implemented
Qucs, as well as other mentioned simulations tools, is a freely available circuit simulators distributed as open source software under the GNU General Public Licence (GPL). The MOS-AK QUCS tutorial has attempted to outline the history and the fundamental features of the QUCS package, the available equation-defined components, built in modelling aids, analysis types and post-simulation data analysis and visualization capabilities. The tutorial reviewed the current position of the ADMS Verilog-A model synthesizer, describing its implementation in the current Qucs release. The talk also introduced how ADMS can be used to develop equation-defined component models of established and emerging technology devices.


The MOS-AK/GSA Modeling Working Group is coordinating several upcoming modeling events to focus on the Verilog-A compact model standardization as well as open source circuit simulation tool developments: 3rd Training Course on Compact Modelling, TCCM, Lublin (PL), a special compact modeling session at the MIXDES'14 Conference in Lublin (PL); an autumn MOS-AK/ESSDERC/ESSCIRC workshop in Venice (I) and MOS-AK Q4 San Francisco (US), Dec. 2014


In the meantime please also visit here where we will continue the discussions of all compact/SPICE modeling topics and its Verilog-A standardization.
 
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