SMIC mainly needs to shrink gate pitch to get to ~10% shy of TSMC's N5 transistor density. Shrinking the metal pitch aggressively (<40 nm) with more extensive multipatterning probably not worth the effort.
The transistor density formula and TSMC N5 numbers are from https://www.angstronomics.com/p/the-truth-of-tsmc-5nm The actual multiplier for the density might be indefinitely debated, but the proportionalities shouldn't be affected. SMIC's 7nm is estimated using TSMC N10.
The transistor density formula and TSMC N5 numbers are from https://www.angstronomics.com/p/the-truth-of-tsmc-5nm The actual multiplier for the density might be indefinitely debated, but the proportionalities shouldn't be affected. SMIC's 7nm is estimated using TSMC N10.
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