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SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

F

Fred Chen

Moderator
TechInsights has completed an exploratory teardown and process analysis of the Huawei Kirin 9030 application processor used in the new Mate 80 Pro Max. Our structural and dimensional analysis confirms that the chip is manufactured using SMIC’s N+3 process, a scaled evolution of its 7nm-class technology, and a key indicator of how close SMIC is to achieving a true 5nm-equivalent node without EUV lithography.

SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm | TechInsights

Our Kirin 9030 analysis confirms SMIC’s N+3 node and reveals how it compares to industry 5nm. Get process measurements, density benchmarks, and expert analysis.
www.techinsights.com www.techinsights.com
 
While SMIC’s N+3 process shows meaningful density improvements, our comparative measurements confirm it remains significantly less scaled than leading commercial 5nm nodes offered by TSMC and Samsung. Full competitive metrics—including gate density comparisons
 
KevinK said:
While SMIC’s N+3 process shows meaningful density improvements, our comparative measurements confirm it remains significantly less scaled than leading commercial 5nm nodes offered by TSMC and Samsung. Full competitive metrics—including gate density comparisons
Click to expand...
I think this characterization by TechInsights is off. The author provided me some key details. I posted only a rough version on X:

https://twitter.com/x/status/1999262408448299219

Maybe a few % is already significant in this context?

They had to go beyond the double patterning of N+2. The metal pitches are close to TSMC N5.
 
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TSMC 5nm is 137 and Samsung 5nm is 126. So you mean 115~125 mtr?

You are calculated by cell height x Gate pitch which provided by Techinsight ?

Or M2 pitch x6=cell height and x gate pitch?
 
semiman said:
AFAIK Samsung's 5nm node is half node of their 7nm EUV process, and TSMC's is full node from their N7. So if SMIC's density is similar to Samsung's then it's more like 7nm-equivalent process.
Click to expand...
I'm just going after the "significantly less scaled" than Samsung "5nm" part.
 
semiman said:
Yes I see that. Anyway I had to delete this comment because the number I knew from TSMC was wrong.
Click to expand...
I went back to check the numbers, what I have is:

Samsung and TSMC 7nm and 5nm.png


I am not sure if SMIC N+2 density was ever released or calculated?
 
LLL0955 said:
N+2 is 93 mtr.

It has 63nm gate pitch and 252nm cell height which revealed by Techinsight.

118 mtr mean ~27% density improve, very huge.
Click to expand...
Yeah, I remembered the gate pitch had been "abnormally" large, but actually it's just that SMIC density < Samsung density < TSMC density for a given process family or cluster.
 
Fred Chen said:
I went back to check the numbers, what I have is:

View attachment 3966

I am not sure if SMIC N+2 density was ever released or calculated?
Click to expand...
Just a spot check, the Semiwiki article on TSMC N5, has:

171 MTr/mm2, but agrees with 51 and 57 gate pitches for N5 and N7 respectively.

semiwiki.com

TSMC N5 Process Technology Wiki - Semiwiki

Overview TSMC N5 (5-nanometer process node) is a high-volume FinFET-based semiconductor manufacturing technology developed by Taiwan Semiconductor Manufacturing Company (TSMC). It succeeded the N7 (7nm) family and introduced substantial improvements in performance, power, and transistor density...
semiwiki.com semiwiki.com
 
Xebec said:
Just a spot check, the Semiwiki article on TSMC N5, has:

171 MTr/mm2, but agrees with 51 and 57 gate pitches for N5 and N7 respectively.

semiwiki.com

TSMC N5 Process Technology Wiki - Semiwiki

Overview TSMC N5 (5-nanometer process node) is a high-volume FinFET-based semiconductor manufacturing technology developed by Taiwan Semiconductor Manufacturing Company (TSMC). It succeeded the N7 (7nm) family and introduced substantial improvements in performance, power, and transistor density...
semiwiki.com semiwiki.com
Click to expand...
This article explained that some discrepancies may arise, depending on the layout assumptions, such as the ratio of NAND to Flip-Flop: https://www.angstronomics.com/p/the-truth-of-tsmc-5nm

I used the formula in that article, but actually I applied it wrongly for the 7nm generation nodes since they were double diffusion break. Here is the correction:

Samsung and TSMC 7nm and 5nm.png


Assuming SMIC has the same double vs. single diffusion break difference, N+3 should be more readily associated with the 5nm crowd.

To get away from these layout assumptions, I'd rather use minimum metal half-pitch as the defining feature, as that sets the main patterning difficulty.

Or maybe cells/um2 (1/gate pitch/cell height)?
 
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