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SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC Is to 5nm

Fred Chen

Moderator
TechInsights has completed an exploratory teardown and process analysis of the Huawei Kirin 9030 application processor used in the new Mate 80 Pro Max. Our structural and dimensional analysis confirms that the chip is manufactured using SMIC’s N+3 process, a scaled evolution of its 7nm-class technology, and a key indicator of how close SMIC is to achieving a true 5nm-equivalent node without EUV lithography.

 
While SMIC’s N+3 process shows meaningful density improvements, our comparative measurements confirm it remains significantly less scaled than leading commercial 5nm nodes offered by TSMC and Samsung. Full competitive metrics—including gate density comparisons
 
While SMIC’s N+3 process shows meaningful density improvements, our comparative measurements confirm it remains significantly less scaled than leading commercial 5nm nodes offered by TSMC and Samsung. Full competitive metrics—including gate density comparisons
I think this characterization by TechInsights is off. The author provided me some key details. I posted only a rough version on X:


Maybe a few % is already significant in this context?

They had to go beyond the double patterning of N+2. The metal pitches are close to TSMC N5.
 
Last edited:
TSMC 5nm is 137 and Samsung 5nm is 126. So you mean 115~125 mtr?

You are calculated by cell height x Gate pitch which provided by Techinsight ?

Or M2 pitch x6=cell height and x gate pitch?
 
AFAIK Samsung's 5nm node is half node of their 7nm EUV process, and TSMC's is full node from their N7. So if SMIC's density is similar to Samsung's then it's more like 7nm-equivalent process.
I'm just going after the "significantly less scaled" than Samsung "5nm" part.
 
Yes I see that. Anyway I had to delete this comment because the number I knew from TSMC was wrong.
I went back to check the numbers, what I have is:

Samsung and TSMC 7nm and 5nm.png


I am not sure if SMIC N+2 density was ever released or calculated?
 
N+2 is 93 mtr.

It has 63nm gate pitch and 252nm cell height which revealed by Techinsight.

118 mtr mean ~27% density improve, very huge.
Yeah, I remembered the gate pitch had been "abnormally" large, but actually it's just that SMIC density < Samsung density < TSMC density for a given process family or cluster.
 
I went back to check the numbers, what I have is:

View attachment 3966

I am not sure if SMIC N+2 density was ever released or calculated?
Just a spot check, the Semiwiki article on TSMC N5, has:

171 MTr/mm2, but agrees with 51 and 57 gate pitches for N5 and N7 respectively.

 
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