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Samsung teases 16-layer 3D DRAM with VCT DRAM as a 'stepping stone' for future RAM

Daniel Nenni

Admin
Staff member
Samsung is pushing into the development of 3D DRAM, the future of compact RAM, announced during its presentation at IMW 2024 this week.

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Samsung is speeding into the world of next-gen 3D RAM, the future of compact RAM, something we're learning from its presentation during IMW 2024 this week.

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VCT (vertical channel transistor) DRAM is one of the first achievements towards this goal, with Samsung expected to complete the initial development of VCT DRAM in 2025, with 3D DRAM hitting the market by 2030. IWM 2024 is an international conference for computer memory companies, where Samsung teased its developments in DRAM innovation.

ZDNet Korea reported on the story, with Samsung Vice President, Lee Si-woo, speaking during Samsung's research in 4F Square VCT DRAM and 3D DRAM. Lee said: "Industrial developments such as hyperscaler AI and on-demand AI require a lot of memory processing ability. On the other hand, the microprocessing technology of existing DRAM is limited". While, in the future, Lee predicts "new innovations are expected to occur in the structure of cells".

One of those innovations is 4F Square VCT DRAM, which is the most compact DRAM design ever. The new 4F Square design uses vertical stacking to reduce DRAM cells by around 30% from today's standard 6F Square DRAM cell structure. 4F Square is not only more horizontally compact, but more power efficient, while its complexity requires extreme precision during fabrication, better materials for production, and more research to get it scalable and mass-producable.

Lee continued, saying: "Many companies are making efforts to transition to 4F Square VCT DRAM. However, for this to happen, the development of new materials such as oxide channel materials and ferroelectrics must take precedence".

The memory industry has been aiming towards vertical DRAM stacking -- including 4F Square -- and eventually, 3D DRAM for the doors to open up for higher capacities and efficiency in DRAM. 3D NAND has excited the memory industry, with Samsung first introducing 3D DRAM (which Samsung calls V-NAND) back in 2013.

Read more: https://www.tweaktown.com/news/9845...t-as-stepping-stone-for-future-ram/index.html
 
Is this vertical memory approach planning to be adopted by Samsung reminiscent to neo-semiconductor monolithic style DRAM, or is it entirely different paradigm using stacked dies that are manufactured separately.
 
Is this vertical memory approach planning to be adopted by Samsung reminiscent to neo-semiconductor monolithic style DRAM, or is it entirely different paradigm using stacked dies that are manufactured separately.
I was at the IMW conference. There are many versions. The 4F2 VCT is an interim, short-term proposed solution, where Samsung also indicated the possible use of the oxide semiconductor channel, just as in IME's 2T0C approach. It can be stacked twice or more monolithically. For many monolithic layers (e.g., 100 or more), there were two proposals similar to 3D NAND. There is Neo Semiconductor's approach which is a floating transistor body DRAM made very similarly to the way 3D NAND is made. Then there is the approach by Samsung called VS-DRAM or VS-CAT, which stores charge in a capacitor that is lying down. This latter structure seems to have more issues though, such as floating body, thermal sensitivity, epitaxial Si channel preferred. Thus, it is expected after the 4F2 VCT.
 
I was at the IMW conference. There are many versions. The 4F2 VCT is an interim, short-term proposed solution, where Samsung also indicated the possible use of the oxide semiconductor channel, just as in IME's 2T0C approach. It can be stacked twice or more monolithically. For many monolithic layers (e.g., 100 or more), there were two proposals similar to 3D NAND. There is Neo Semiconductor's approach which is a floating transistor body DRAM made very similarly to the way 3D NAND is made. Then there is the approach by Samsung called VS-DRAM or VS-CAT, which stores charge in a capacitor that is lying down. This latter structure seems to have more issues though, such as floating body, thermal sensitivity, epitaxial Si channel preferred. Thus, it is expected after the 4F2 VCT.
I wish I had like 5-10 more years experience and was in the memory side of things. The transition from 2D to 3D is a huge paradigm switch that I think could end up looking similar to logic HKMG. The path forward is non obvious and the winners/losers of the DRAM industry will be determined by finding the pitfalls. Micron's planar DRAM lead means practically nothing in this new world order, and the cost per bit implications could actually kill smaller guys like SK-H or Micron if a gate first level slip up happened (although given past events the death of SK-H can never be assumed to be its actual death). If a big screw happened to only Samsung then their larger scale would become a pair of ankle weights that drown them rather than acting as a club to bludgeon their competitors as their RAM would be completely cost ineffective.

Wait too long and you die from your obsolete planar DRAM. Go too early and you might be stuck with a poor architecture that screws you over when your competitors eventually develop a more cost effective process with faster ramping yields (like IMFT and their FG 3D-NAND vs ROW's more scalable/cheaper CTF 3D-NAND).
 
I am not in this line , but if this is say the best methodology for doing something can it not just be copied , or tweaked a bit by others?

What is the benefit to Samsung or anyone for that matter to announce something like this?
 
I am not in this line , but if this is say the best methodology for doing something can it not just be copied , or tweaked a bit by others?

What is the benefit to Samsung or anyone for that matter to announce something like this?
The proposals have been around for some time, and issues are still present. So it's more like reporting on development progress.
 
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