Samsung finally kicks off the GAA Age

[nghanayem]

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It may be smaller than 18mm^2, have transistors that look horrendous, and lack an inner spacer. But it is a fully featured SOC that does have SRAM (funnily enough even denser than even N5 or N3E), DDR, analog, multiple device widths, what appear to be multiple VTs (on this point I need to wait for the full analysis to fully confirm what my eyes see), and this is an actual high volume product that will be made in the many millions of units. By my books that joke of a bitcoin mining ASIC did not count. However with this accomplishment I think Samsung can finally lay claim to having the first commercial GAA product with their SF3/3GAP process. While Samsung has in the past been the first foundry to manufacture products with new transistor architectures (such as with finFET), this is the first time they have been first in industry to lead on a new transistor level innovation. In spite of all the work Samsung has ahead of themselves to correct the flaws with SF3, I think they deserve some recognition for this big accomplishment.

 

[Fred Chen]

Samsung SF3 (2nd Gen 3nm GAA) in Exynos W1000 Processor Confirmed | TechInsights

Initial SEM results confirm Samsung’s 2nd generation 3nm GAA technology in the Exynos W1000 processor. Discover key insights and implications for high-volume manufacturing requirements in our latest analysis on the TechInsights Platform.

www.techinsights.com

Initial SEM results for the Exynos W1000 processor, now available on the TechInsights platform, confirm Samsung’s successful implementation of 2nd generation 3nm GAA technology. This advancement marks a significant milestone in semiconductor technology, showcasing Samsung’s ability to push the boundaries of chip design and manufacturing.

SEM cross-section images reveal nanosheets at the gate level, providing clear evidence of Samsung’s SF3 technology in action. The gate-level die photograph further illustrates the processor's core components: a high-performance single-core Arm Cortex-A78 CPU, a high-efficiency quad-core Arm Cortex-A55 CPU, and a dual-core Arm Mali-G68 GPU. These components confirm the robust design and integration capabilities of the Exynos W1000 processor, highlighting Samsung's expertise in developing advanced SoCs.

Our ongoing analysis will deliver more insights on the SF3 node, including detailed measurements of critical dimensions. Samsung's achievement as the first to produce gate-all-around technology in a consumer product, albeit in a lower-volume smartwatch, sets the stage for potential expansion into higher-volume devices. The critical question remains: can Samsung optimize this process for their next flagship smartphone, the Galaxy S25+, and meet the stringent demands of high-volume manufacturing? Stay tuned as we continue to uncover the capabilities and future implications of Samsung's groundbreaking technology.

 

[chenyj]

Samsung SF3 (2nd Gen 3nm GAA) in Exynos W1000 Processor Confirmed | TechInsights

Initial SEM results confirm Samsung’s 2nd generation 3nm GAA technology in the Exynos W1000 processor. Discover key insights and implications for high-volume manufacturing requirements in our latest analysis on the TechInsights Platform.

www.techinsights.com

Initial SEM results for the Exynos W1000 processor, now available on the TechInsights platform, confirm Samsung’s successful implementation of 2nd generation 3nm GAA technology. This advancement marks a significant milestone in semiconductor technology, showcasing Samsung’s ability to push the boundaries of chip design and manufacturing.

SEM cross-section images reveal nanosheets at the gate level, providing clear evidence of Samsung’s SF3 technology in action. The gate-level die photograph further illustrates the processor's core components: a high-performance single-core Arm Cortex-A78 CPU, a high-efficiency quad-core Arm Cortex-A55 CPU, and a dual-core Arm Mali-G68 GPU. These components confirm the robust design and integration capabilities of the Exynos W1000 processor, highlighting Samsung's expertise in developing advanced SoCs.

Our ongoing analysis will deliver more insights on the SF3 node, including detailed measurements of critical dimensions. Samsung's achievement as the first to produce gate-all-around technology in a consumer product, albeit in a lower-volume smartwatch, sets the stage for potential expansion into higher-volume devices. The critical question remains: can Samsung optimize this process for their next flagship smartphone, the Galaxy S25+, and meet the stringent demands of high-volume manufacturing? Stay tuned as we continue to uncover the capabilities and future implications of Samsung's groundbreaking technology.

The SEM picture publicly shown on TechInsights platform was blurred and doesn't have a scale bar. But we can still see the 3-nanosheet structure without bottom dielectric layer. Besides that, the immediate impression is Samsung's nanosheet is too thick (only slightly thinner than the nanosheet width) and the leakage will be a serious issue (hard to control short-channel effect and leakage). Typically, the optimized NS width and thickness for 2-3nm node is about 30nm and 6-7nm, respectively. It's unclear why they are doing so differently. Thicker NS will help mobility and on-state current, while it's not quite possible such a device design can be used for low-power applications. There is a contacted structure (dummy?) between two NS stacks and we don't see a similar structure in FinFET. The M0 metal pitch looks huge, but metal space/gap is unusually small, showing a characteristic of downward self-aligned via process (SAV), possibly with EUV SADP/SALELE technique? It's less likely patterned by single-exposure EUV due to the patterning difficulty in controlling small dielectric line for metal gap and incorporating downward SAV process. Looks more like a downgraded GAA design (for a smartwatch) rather than a typical 2-3nm GAA logic design (e.g. with a metal pitch of ~22nm).

 

[siliconbruh999]

The critical question remains: can Samsung optimize this process for their next flagship smartphone, the Galaxy S25+, and meet the stringent demands of high-volume manufacturing? Stay tuned as we continue to uncover the capabilities and future implications of Samsung's groundbreaking technology.

I am pretty sure even samsung doesn't know that yet

 

[nghanayem]

The SEM picture publicly shown on TechInsights platform was blurred and doesn't have a scale bar. But we can still see the 3-nanosheet structure without bottom dielectric layer. Besides that, the immediate impression is Samsung's nanosheet is too thick (only slightly thinner than the nanosheet width) and the leakage will be a serious issue (hard to control short-channel effect and leakage). Typically, the optimized NS width and thickness for 2-3nm node is about 30nm and 6-7nm, respectively. It's unclear why they are doing so differently.

The blurred image is not a fin cut it is a gate cut. The thin strips of grey between the boxes are the nanosheets. The thick metal lines with very little space is the M1 and M3 with the M0 and M2 being the flat white lines. With that said I think the SF3E sheets might have been thinner than the SF3 sheets, but I don't remember for sure. Looking at SF3E there were a lot of bent and pinched off nanosheets, maybe this was to add more structural rigidity so the FETs could survive whatever torture Samsung is putting those wafers under during nanowire release? Also as you mentioned it could be that Samsung needed more drive and that is why the sheets are so thick.

Thicker NS will help mobility and on-state current, while it's not quite possible such a device design can be used for low-power applications. There is a contacted structure (dummy?) between two NS stacks and we don't see a similar structure in FinFET. The M0 metal pitch looks huge, but metal space/gap is unusually small, showing a characteristic of downward self-aligned via process (SAV), possibly with EUV SADP/SALELE technique? It's less likely patterned by single-exposure EUV due to the patterning difficulty in controlling small dielectric line for metal gap and incorporating downward SAV process.

In the full report it is pretty obvious what Samsung is doing and Techinsights also explicitly calls it out, but I will leave it at that out of respect for Techinsights' work.

Looks more like a downgraded GAA design (for a smartwatch) rather than a typical 2-3nm GAA logic design

I think you are being a bit too harsh. Yes the density is not as dense as the N3E 2-1 fin mixed row library. But from what I see it is very competitive with the stand alone 2 fin cell and 2-2 fin mixed row cells, and with an even denser SRAM bitcell than TSMC (with that said I wouldn't be shocked if full SRAM array+periphery is denser for TSMC though). My opinion is that SF3 is without a doubt a 3"nm" class node, just that it likely is the lowest power performance 3"nm" node given how far behind SF4E/SF4/SF4P are compared to N4P in those metrics. Considering the transition from 3"nm to "2"nm" class nodes are just TSMC and Intel's insertion for GAA and BSPDN (similar to 22/20nm and 16/14nm where the only difference was adding finFET with the same BEOL and a marginal cell size reduction); I think it would be fair game to dub a significantly more refined intranode improvement of SF3 as SF2 especially if Samsung can deliver the promised BSPD option later down the line.

(e.g. with a metal pitch of ~22nm).

By this logic TSMC N7 was not a 7"nm" class node because the MMP was 40nm not 36nm like with intel and Samsung. MMP is just a tool to get some amount of density, if you can get to a density becoming of a certain node class without pulling the pitch scaling lever (eg COAG, finFLEX, SDB, BSPDN, etc) that is all the better for the PPAC. Also MMP for N3 is 23nm not 22nm.

 

[chenyj]

The blurred image is not a fin cut it is a gate cut. The thin strips of grey between the boxes are the nanosheets. The thick metal lines with very little space is the M1 and M3 with the M0 and M2 being the flat white lines. With that said I think the SF3E sheets might have been thinner than the SF3 sheets, but I don't remember for sure. Looking at SF3E there were a lot of bent and pinched off nanosheets, maybe this was to add more structural rigidity so the FETs could survive whatever torture Samsung is putting those wafers under during nanowire release? Also as you mentioned it could be that Samsung needed more drive and that is why the sheets are so thick.

In the full report it is pretty obvious what Samsung is doing and Techinsights also explicitly calls it out, but I will leave it at that out of respect for Techinsights' work.

I think you are being a bit too harsh. Yes the density is not as dense as the N3E 2-1 fin mixed row library. But from what I see it is very competitive with the stand alone 2 fin cell and 2-2 fin mixed row cells, and with an even denser SRAM bitcell than TSMC (with that said I wouldn't be shocked if full SRAM array+periphery is denser for TSMC though). My opinion is that SF3 is without a doubt a 3"nm" class node, just that it likely is the lowest power performance 3"nm" node given how far behind SF4E/SF4/SF4P are compared to N4P in those metrics. Considering the transition from 3"nm to "2"nm" class nodes are just TSMC and Intel's insertion for GAA and BSPDN (similar to 22/20nm and 16/14nm where the only difference was adding finFET with the same BEOL and a marginal cell size reduction); I think it would be fair game to dub a significantly more refined intranode improvement of SF3 as SF2 especially if Samsung can deliver the promised BSPD option later down the line.

By this logic TSMC N7 was not a 7"nm" class node because the MMP was 40nm not 36nm like with intel and Samsung. MMP is just a tool to get some amount of density, if you can get to a density becoming of a certain node class without pulling the pitch scaling lever (eg COAG, finFLEX, SDB, BSPDN, etc) that is all the better for the PPAC. Also MMP for N3 is 23nm not 22nm.

Indeed, that blurred image is a gate cut, which helps to answer my questions as well. The gray boxes should be metal gates and dark layers between the boxes should be NS, whose thickness will be thinner than what I thought before. I should have been able to tell this if more attention was paid to the main spacer + top gate structure. And yes, I did follow the TSMC node definition rather than Intel or Samsung's.

 

[lefty]

I'm guessing that yields aren't so good if they only can produce a 18mm^2 die

 

[Fred Chen]

I'm guessing that yields aren't so good if they only can produce a 18mm^2 die

Possibly the W1000 can help give a yield preview ahead of the Exynos 2500: https://9to5google.com/2024/08/01/samsung-exynos-2500-galaxy-s25-plans/

 

[nghanayem]

I'm guessing that yields aren't so good if they only can produce a 18mm^2 die

That is a very safe assumption when you look at the TEMs. There are some very ugly transistors. But compared to SF3E from last year it is SO MUCH better. When I was going through those SF3E images recently I was clutching my side laughing that a released product could look so bad that you would think the process was in a PDK 0.01 state. One of the thoughts I also had was how is this somehow even worse than I remembered it being. SF3 looks similar to or maybe a bit better than what I remember TI's cannon lake TEMs looking like, and definitely worse than what I remember TI's broadwell TEMs. TLDR a lot of improvements have been made, and in a year the process looks like it should be able to get to a broadwell or Icelake level (ie in a healthy enough state for an Exynos next year). Then from there have SF3 family (which I guess includes SF2) in a reasonable state for QCOM in like 2026 and beating MTK/QCOM N2 mobile APs to market?