Samsung Electronics reduces the number of EUV layers in 1c DRAM... Yield 'Focus'

[Fred Chen]

Seyeon Lee 2025.03.19 07:00:37

The number of EUV layers will be reduced by 30% compared to the plan 2~3 years ago

Samsung Electronics, which is making an all-out effort to secure yields, has decided to reduce the number of layers of extreme ultraviolet (EUV) lithography equipment from the original plan. In the 10nm-class 6th generation (1c) DRAM, the plan to add an EUV application layer was revised, and in the 7th generation (1d) DRAM, the growth rate is said to have slowed down significantly.

It is inevitable that the number of EUV layers itself will increase as the transition to the state-of-the-art process increases, but it is analyzed that the plan has been partially modified as the difficulty of the subsequent process has increased along with it. If the number of layers decreases, the cost competitiveness itself decreases. However, since the introduction of EUV, the depreciation and cost burden on infrastructure investment have increased due to the decrease in yield, so the company plans to reduce the cost in the long term by increasing the yield.

According to the industry, EUV is a lithography equipment that projects light using a light source with extreme ultraviolet wavelengths in the semiconductor manufacturing process, and it is a technology necessary to engrave microscopic circuits on wafers. EUV light sources have a shorter wavelength than argon fluoride (ArF) light sources used in conventional processes, which has the advantage of being able to engrave patterns much more finely. In addition, in the existing process, it was necessary to repeat the lithography process several times to engrave the microcircuit, but EUV has the effect of increasing productivity by drastically reducing these process steps.

An industry insider said, "Samsung Electronics has recently reduced the number of EUV layers by about 30% compared to what was planned 2~3 years ago" and added, "Originally, we planned to use 8~9 EUV layers in 1C DRAM, but we are trying to keep it at the level of 6~7 (currently known). In the case of 1D DRAM, the increase in EUV layers appears to be even more significant."

The reason for the reduction of EUV layers is that as the number of layers increases, the process becomes more complex and it becomes difficult to increase stability. The advantage of using EUV is that it can control the number of process steps and implement circuit patterns more finely, but as the number of EUV application layers increases, the difficulty of subsequent processes increases dramatically. As a result, Samsung Electronics is also moving in the direction of reducing its reliance on EUV in consideration of stability.

"In the case of DRAM, it is necessary to draw a circuit finely using EUV in the exposure process, and then remove unnecessary parts of the circuit in the etching process (which is the subsequent process)," the previous official said, adding, "However, the finer the circuit, the more difficult the removal work becomes. The more layers EUV applied, the more detailed technology is required, so we are trying to reduce the amount of use."

There is also an intention to reduce the cost burden due to the decline in yield. Samsung Electronics recently switched to the 1C process, and when the yield was at a low level, it began to change the design of the 1C DRAM. In this process, the chip size is larger than originally planned, and instead of giving up some of the productivity, the company is trying to improve the degree of completion.

In a situation where there is already a cost burden due to a decrease in productivity, it is evaluated that increasing the EUV application layer does not necessarily improve performance and reduce costs. If the yield rate drops due to the company's lack of technology, it may have the opposite effect, such as increasing the cost, so Samsung Electronics seems to have chosen to reduce the existing cost by reducing the number of EUV layers compared to the original plan.

In fact, Samsung Electronics is expected to take a cautious approach to introducing new equipment as it has secured enough EUV equipment. For now, it is expected that the company will make the most of its idle equipment and proceed towards the purchase of a small addition to new equipment. An official from the securities industry said, "It costs about 3,000~500 billion won per EUV device, and if we reduce it, we can reduce depreciation expenses as well," adding, "There are so many processes in DRAM that EUV is not everything that determines the price, but there is a positive part in reducing the cost as it has a lot of impact."

Samsung Electronics has been criticized for unreasonably introducing new technologies and advanced processes in the face of competitors, which negatively affected stability and yield. The 10nm-class DRAM process technology is being developed in the following order: 1x (1st generation), 1y (2nd generation), 1z (3rd generation), 1a (4th generation), 1b (5th generation), and 1c (6th generation), and Samsung Electronics has been gradually expanding the EUV process from 1z DRAM to a single layer. However, since EUV was an early-stage technology at the time, it was difficult to secure yield, and it is analyzed that the aftermath continued until the 1c process.

On the other hand, SK hynix, which delayed the introduction of equipment, actually increased its profit margin and improved its yield. A Samsung Electronics official said, "Internally, there are voices of self-reflection about the unreasonable introduction of EUV in DRAM."

Meanwhile, SK hynix, a competitor, has introduced EUV equipment for DRAM since 2021 and is gradually increasing the utilization of EUV equipment as the process is advanced to 1a→1b→1c. Micron also introduced new EUV equipment from 1γ (corresponding to gamma and 1c), and it is known that it is currently only applied to one layer.

Lee Se-yeon leesy@dealsite.co.kr

(c) Look at the market with fresh eyes. All rights reserved.

Translated from https://dealsite.co.kr/articles/138336

 

[Fred Chen]

Fewer but newer steps does not necessarily mean better yield; it totally depends on what the step is. That is why we don't just jump on nanoimprint.

 

[Artificer60]

This one has me scratching my head. You don't get to just eliminate Litho layers. If you don't use EUV you have to use DUV and you will need more DUV steps to achieve the same resolution. How this leads to improved yield is beyond me.

If I'm not mistaken much of Intel's fall from grace was attributed to a failure to incorporate EUV on 10nm and having to rely on using DUV lithography steps which led to yield challenges.

 

[Fred Chen]

This one has me scratching my head. You don't get to just eliminate Litho layers. If you don't use EUV you have to use DUV and you will need more DUV steps to achieve the same resolution. How this leads to improved yield is beyond me.

If I'm not mistaken much of Intel's fall from grace was attributed to a failure to incorporate EUV on 10nm and having to rely on using DUV lithography steps which led to yield challenges.

For DRAM, there is no rapid increase in mask count as seen with logic. Instead there are changes such as from direct print to SADP to SAQP, but these are long established processes (for the DRAM/Flash makers). There was a mention of combining some array patterns with peripheral patterns in one exposure, but the design rules are so different, the illuminations aren't compatible.

Logic such as by Intel or TSMC has quite a few cut and via patterns which drive mask increases, but this was also required for EUV shortly after.

 

[nghanayem]

This one has me scratching my head. You don't get to just eliminate Litho layers. If you don't use EUV you have to use DUV and you will need more DUV steps to achieve the same resolution. How this leads to improved yield is beyond me.

Besides what Fred said about DRAM not living in the same layout hell as logic (with all of the cuts and logic that entails), you must remember that DRAM is much denser than logic. Like 20-22nm min feature size versus 28nm and only recently 23nm. Layouts are also WAY denser too. EUV can paint fine lines. But it is like if the painter has shakey hands. For ultra fine DRAM where uniformity has a HUGE impact on bit reliability, refresh time, and power this is an important concern. If the higher DD or lower parametric yield from fewer steps exceeds the sum of lower DD larger number of steps. Then the more complex process will be better for yield.

If I'm not mistaken much of Intel's fall from grace was attributed to a failure to incorporate EUV on 10nm and having to rely on using DUV lithography steps which led to yield challenges.

A gross oversimplification that also ignores that N7 never used EUV and 7LP didn't use EUV and losses all nuance.

Logic such as by Intel or TSMC has quite a few cut and via patterns which drive mask increases, but this was also required for EUV shortly after.

Not really for Intel since 4/3 uses EUV for features easily in the direct print regime, and 20/Intel 4+powervia have min metal pity that is the same as intel/Samsung 7. According to Mark Phillips 18A has a very limited use of double patterned EUV but for T2T reasons not for resolution without specifying if it was LELE (used at Intel before), SAPD (used at Intel before), or SALELE (would be new to Intel).

For TSMC very much so since N5 M0 went past the regime for easy direct print, but M1 and above (34+nm) shouldn't have been too hard. Obviously with N3 and N3E families TSMC had a lot more SALELE and I wouldn't be shocked if the number of blocks had to increase. But FWIW even at 23nm EUV would be using way fewer blocks than DUV SAPQ (my guessestimate would be 1/3 or 1/4 the number of blocks). You also would make Etch's life a living nightmare with all of the different materials and spacers you need to cut through. And who would want to do that (trick question everyone)

FEOL EUV use is a bit trickier to nail down than BEOL/MEOL (at least for a BEOL person like myself). Probably the premier and most difficult EUV application is doing poly cut post RMG on N5/N3E. But a lot of that difficulty is overlay. LER and the thinness of the cut are also critical because you want uniform gate end caps and to have enough space for all of your WFMs inside the gate. But I suspect that DUV SAPQ is too coarse and inflexible for that application to really entertain the idea of using that instead of EUV LELE or SALELE (if for the purposes of this discussion we assume N3E isn't just using direct print EUV for that application).