S
Shyam Ramaswamy
Guest
If you are a Verification professional, you cannot afford to miss the Verification Futures conference on 19[SUP]th[/SUP] March 2013 at Hotel Royal Orchid, Bangalore. The who’s-who of the Verification industry will be in attendance presenting, discussing and resolving those complex verification problems that you always wanted a solution to.
Broadcom will be presenting a user paper on reducing chip level verification effort by optimizing gate level simulation runs and using package aware testbenches. The novel techniques suggested in this paper make it is a must-attend for Verification managers aiming to achieve quicker verification closure times.
From NXP, Mr. Sainath will present a challenge paper that provides insights into reducing verification turnaround times at module, sub-system and system levels. This paper will be very useful to those aiming to develop a scalable, co-verification enabled system level verification environment.
We also have Verification specialists, Mr. Mark Olen from Mentor Graphics and Mr. Jacek Majkowski from Aldec presenting on two exciting topics - Technology evolution in Functional Verification and Standard Co-Emulation Modeling Interface (SCE-MI) respectively. From the EDA side, Cadence and Synopsys have already confirmed participation.
With over 180 senior Verification professionals already expressing interest in participation, seats are running out fast. For those unable to attend the event live, we are providing webinar facility also.
Put an end to your verification problems! Register now!
Broadcom will be presenting a user paper on reducing chip level verification effort by optimizing gate level simulation runs and using package aware testbenches. The novel techniques suggested in this paper make it is a must-attend for Verification managers aiming to achieve quicker verification closure times.
From NXP, Mr. Sainath will present a challenge paper that provides insights into reducing verification turnaround times at module, sub-system and system levels. This paper will be very useful to those aiming to develop a scalable, co-verification enabled system level verification environment.
We also have Verification specialists, Mr. Mark Olen from Mentor Graphics and Mr. Jacek Majkowski from Aldec presenting on two exciting topics - Technology evolution in Functional Verification and Standard Co-Emulation Modeling Interface (SCE-MI) respectively. From the EDA side, Cadence and Synopsys have already confirmed participation.
With over 180 senior Verification professionals already expressing interest in participation, seats are running out fast. For those unable to attend the event live, we are providing webinar facility also.
Put an end to your verification problems! Register now!
