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Array
(
    [content] => 
    [params] => Array
        (
            [0] => /forum/threads/question-about-the-approach-to-the-sub-10-nm-lithography-nodes.8300/
        )

    [addOns] => Array
        (
            [DL6/MLTP] => 13
            [Hampel/TimeZoneDebug] => 1000070
            [SV/ChangePostDate] => 2010200
            [SemiWiki/Newsletter] => 1000010
            [SemiWiki/WPMenu] => 1000010
            [SemiWiki/XPressExtend] => 1000010
            [ThemeHouse/XLink] => 1000970
            [ThemeHouse/XPress] => 1010570
            [XF] => 2021770
            [XFI] => 1050270
        )

    [wordpress] => /var/www/html
)

Question about the approach to the sub-10 nm lithography nodes

M

mhagmann

Member
In present art the dopant concentration corresponds to a carrier mean-free-path on the order of 10 nm. However, at the sub-10 nm nodes will it be necessary to increase the dopant concentration in order for the carriers to respond to the finer semiconductor structures, or will the metallic parts be sufficient to obtain this finer control? I ask this because, if the dopant concentration is increased at each successive node, there will be a need for much finer (sub-nm) resolution in measuring the carrier concentration. Perhaps sub-nm resolution could be accomplished by an extension of SSRM (scanning spreading resistance microscopy) because the concept of "resistance" would be valid at the smaller distances due to the reduction in their mean-free-path.
 
In my opinion, it is not a problem. Most difficult part for sub 10 S/D engineering is thermal budget. We have enough dopants there. They just need to be activated. Resistance won't shoot up as features keep scaling, at least before 3nm. However capacitance is more difficult to deal with.
 
Li Yisuo said:
In my opinion, it is not a problem. Most difficult part for sub 10 S/D engineering is thermal budget. We have enough dopants there. They just need to be activated. Resistance won't shoot up as features keep scaling, at least before 3nm. However capacitance is more difficult to deal with.
Click to expand...

Probably the most difficult part is to get a spatial distribution of active dopant density in the channel direction (this determines junction location) and its variation along the fin height. Back in the planar days you could get a reasonable estimate of this just from electrical parameters, like series resistance vs overlap capacitance plots for different process splits. Fin brings in the possibility of variation along the height and complicates the analysis. What makes physical measurements difficult is that the junction is buried under spacer/gate and unless you remove them or make a cross section just in the middle of the fin is not accessible.

Here is an example of what can be done today:

Scanning spreading resistance microscopy-imec

For a planar device (last picture), it's easy to make a cross section of the transistor in the middle of the channel. For a FinFET a similar cross section is not shown. What they are showing in that page (second picture) is a cross section normal to fin (not along the fin) presumably for a very long S/D device. This is not something I am interested in seeing.
 
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