You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!
[table] style="width: 100%"
|-
| colspan="3" |
|-
| style="width: 11%" |
| width="85%" |
| width="4%" |
|-
|
| Cadence introduces the first-ever verification IP (VIP) to support the new MIPI SoundWire and MIPI C-PHY specifications.
You can now simplify the pre-silicon verification of your next mobile SoC design with these new VIP.
Learn about the full line of Cadence VIP for MIPI Protocols supporting all these MIPI interfaces: C-PHY, CSI-2, CSI-3, DBI, DigRF, D-PHY, DSI, LLI 2.0, M-PHY, SLIMbus, SoundWire, and UniPro.
Also, Cadence is working on leading-edge audio DSP and interface IP.
Look at the article at this link https://www.semiwiki.com/forum/cont...h-performance-low-power-audio-subsystems.html
which describes audio subsystem architecture based on DSP-tunneled model for audio data transport and audio interface IP that uses the new Soundwire standard from MIPI.