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There are lots of things you could do in analog instead of digital, but I don't think the tool flow is up to the job - I've been working on it for a long time, and filling in the gap between SPICE and Verilog (for verification) has been very slow going.
Simguru, from the looks of what they are doing , they design a block that to the outside world looks digital while inside it's analog. since it's a single block , maybe they just design everything in spice.
So than you could maybe design your whole system in a verilog model.
But that leaves the question - how do they manage noise ? Can they build some EDA tool to help with that ?
There are ways to do digital simulation handling variability where you can include stuff like BER at non-zero levels, and you can use Verilog-AMS to do it.
Verilog-AMS also handles behavioral analog modeling, so you can do it that way to.
Some people are working on ways to automate converting analog models (SPICE/Verilog-A) to discrete real-number models for VHDL/SystemVerilog, but the methodology is not as automatic as Verilog-AMS (can be).