Need information regarding Tapeout

[ramesh_dasara]

Hi everyone,

I am working for one the EDA distributor in India. I work for University tea where we support universities in using the EDA tool for their project work & paper implementations.

Some of my clients in premier institutes were interested in taking their GDSII to tapeout.

Can I know which of the fabricators are ready give a free wafer space to the Universities & what will be the best time in a year to ask fabs for the space?

regards,

RamesH

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[Daniel Payne]

I'm not sure about free wafer space however I do know that MOSIS offers multi-project wafers to lower the costs of fabrication.

How about using FPGA devices instead of COT?

 

[ramesh_dasara]

Hi Daniel,

Thanks for the reply.

For a digital logic, I can go for FPGA, but there are some designs where we are implementing them in Full Custom IC flow.

Does MOSIS has a PDK that supports Mentor graphics IC design tools (Design Architect & ICstation)?

Can I contact TSMC / any other fab for PDK, such that I will send only GDSII to the MOSIS( I couldnot see PDK for Mentor tools in MOSIS site)?

Does MOSIS support in this way of accepting only GDS?

regards,

RamesH

 

[SZA]

Hi Ramesh

You can also have a look at CMP (CMP: Circuits Multi-Projets) and Europractice (Europractice Homepage). Universities/research labs in Europe frequently use them for test chips (digital/analog/mixed).

 

[ramesh_dasara]

Hi SZA,

Thanks for this, Let me contact CMP.

What does IMEC do? Does they to support the tape out solutions for univ??

regards,

RamesH

 

[SZA]

Hi Ramesh
IMEC is a big research entity which also manages i guess operation of Europractice (Europractice Homepage). Like CMP is also in wide sense managed by Research lab of Grenoble University. Both CMP and Europractice are well known and reputed.
The best for you is to contact directly CMP/Europractice and discuss with them your requirements.

 

[harpoon]

Hi Daniel,

Does MOSIS has a PDK that supports Mentor graphics IC design tools (Design Architect & ICstation)?

RamesH

MOSIS accepts GDS2 as the design input. With regards to TSMC and PDKs, you will need to contact Mentor to get help on this. TSMC uses iPDKs for their newer processes ... 0.13um and smaller but may need a "extra work" from Mentor to make it useable.

To make things more complicated, Mentor is now (past year or so) rolling out a new set of IC tools, V9 and V10. Getting the PDKs translated to their old tools (DAIC, ICStation, ICStudio) will probably take a very long time or not recommended at all.

Hope this helps ...